Prosecution Insights
Last updated: October 02, 2026
Application No. 18/739,367

SEMICONDUCTOR STRUCTURE

Non-Final OA §102§Other
Filed
Jun 11, 2024
Priority
May 13, 2024 — TW 113117627
Examiner
HARRISTON, WILLIAM A
Art Unit
Tech Center
Assignee
United Microelectronics Corp.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
965 granted / 1078 resolved
+29.5% vs TC avg
Moderate +8% lift
Without
With
+8.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
19 currently pending
Career history
1094
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
45.9%
+5.9% vs TC avg
§102
33.5%
-6.5% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1078 resolved cases

Office Action

§102 §Other
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Information Disclosure Statement The information disclosure statement filed on 06/11/2024 has been considered. Drawings The drawings filed on 06/11/2024 are acceptable. Specification The abstract of the disclosure and the specification filed on 06/11/2024 are acceptable. Claim Objections Claim 15 objected to because of the following informalities: claim 15 recites “…wherein the gate structure overlaps the isolation structure, and the gate structure partially overlaps the isolation structure the third well”. It appears that there is a typo. Appropriate correction is required. Claim Rejections - 35 USC § 102 (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 4, 10, 11, 13, 14, 16, 20 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lin (US 2015/0187933). PNG media_image1.png 530 574 media_image1.png Greyscale Regarding claim 1, Lin (US 2015/0187933) discloses: A semiconductor structure, comprising: a substrate (302, ¶0025); a first well (330, ¶0027) in the substrate (302) and having a first side surface; a second well (340, ¶0027) in the substrate and having a second side surface; a third well (344, ¶0027) in the substrate (302), wherein the second well (340) is between the first well (330) and the third well (344); an isolation structure (310, ¶0026) in the substrate (302) and between the first well (330) and the second well (340); a drain region (332, ¶0027) in the first well (330); a source region (342, ¶0027) in the third well (344); and a gate structure (320, 322, 324, ¶0026) on the substrate, wherein the first side surface of the first well (330) faces the second side surface of the second well (340), and the first side surface of the first well (330) is apart from the second side surface of the second well (340). Regarding claim 2, Lin further discloses: wherein the first well (330) has a first conductivity type (¶0027), the second well (340) has the first conductivity type, and the third well has a second conductivity type different from the first conductivity type (¶0027). Regarding claim 4, Lin further discloses: wherein the isolation structure (310) has a first sidewall and a second sidewall opposite to the first sidewall, and a distance between the second sidewall and the second side surface of the second well (340) is greater than zero. Regarding claim 10, Lin further discloses: wherein at least a portion of a lower surface of the isolation structure (310) is not covered by the first well (330) and the second well (340). Regarding claim 11, Lin further discloses: wherein at least a portion of a lower surface of the isolation structure (310) directly contacts the substrate. Regarding claim 13, Lin further discloses: wherein current flows from the source region to the drain region through the third well, the second well, the substrate and the first well. Regarding claim 14, Lin further discloses: wherein a lower surface of the isolation structure (310) is higher than a lower surface of the first well (330) and a lower surface of the second well (340). Regarding claim 16, Lin further discloses: wherein the second well adjoins (340) the third well (344). Regarding claim 20, Lin further discloses: wherein the first side surface of the first well (330) and the second side surface of the second well (340) are covered by the substrate (302). Allowable Subject Matter Claims 3, 5-9, 12, 15 and 17-19 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 3, the prior art does not disclose “wherein the isolation structure comprises a first portion overlapping the first well in a longitudinal direction and a second portion overlapping the second well in the longitudinal direction” in combination with the remaining claimed features. Regarding claim 5, the prior art does not disclose “wherein the first sidewall of the isolation structure is covered by the first well, and the second sidewall of the isolation structure is covered by the second well” in combination with the remaining claimed features. Regarding claim 7, the prior art does not disclose “wherein the isolation structure has a first sidewall and a second sidewall opposite to the first sidewall, a distance between the first sidewall and the first side surface of the first well is equal to zero, and a distance between the second sidewall and the second side surface of the second well is equal to zero” in combination with the remaining claimed features. Regarding claim 9, the prior art does not disclose “wherein the isolation structure has a first sidewall and a second sidewall opposite to the first sidewall, the first side surface of the first well is aligned with the first sidewall of the isolation structure in a longitudinal direction, and/or the second side surface of the second well is aligned with the second sidewall of the isolation structure in the longitudinal direction” in combination with the remaining claimed features. Regarding claim 12, the prior art does not disclose “, wherein the isolation structure has a first sidewall and a second sidewall opposite to the first sidewall, a distance between the first sidewall and the first side surface of the first well is equal to a distance between the second sidewall and the second side surface of the second well” in combination with the remaining claimed features. Regarding claim 17, Lin does not disclose “a doping region and another isolation structure in the third well, wherein the doping region and the source region are separated by the another isolation structure” in combination with the remaining claimed features. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM A HARRISTON/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jun 11, 2024
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §102, §Other (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751077
FLIP-CHIP FIELD EFFECT TRANSISTOR LAYOUTS AND STRUCTURES
3y 7m to grant Granted Sep 29, 2026
Patent 12751326
STACKED CHIP SCALE SEMICONDUCTOR DEVICE
3y 2m to grant Granted Sep 29, 2026
Patent 12745478
RADIATION DETECTOR FOR POSITION-RESOLVED DETECTION OF RADIATION
2y 5m to grant Granted Sep 22, 2026
Patent 12740420
STRUCTURE FOR DELAMINATION MITIGATION IN A SEMICONDUCTOR DEVICE
3y 1m to grant Granted Sep 15, 2026
Patent 12740441
SEMICONDUCTOR PACKAGE
2y 9m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
98%
With Interview (+8.5%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1078 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month