DETAILED ACTION
The Amendment filed April 07, 2026 has been entered. Claims 1-20 are pending. Claim 4 has been cancelled. Claim 21 has been added. Claims 1, 8 and 15 are independent.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-21 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jain (US 2022/0336009) in view of Desai et al. (US 9,520,165).
Regarding independent claims 1, 8 and its method independent claim 15, Jain teaches a device (see e.g., FIG. 3) comprising:
a memory array circuit (346 … 348) configured to store data therein;
a global input/output (I/O) circuit (250) configured to receive or transmit the data;
a local I/O circuit (230) configured to transfer the data between the memory array circuit and the global I/O circuit and including:
complementary read bit lines (RBLB); and
a sense amplifier and read bit line pre-charger circuit (322) connected between the complementary read bit lines and configured to receive a complement sense amplifier pre-charge signal (SAPRB) (see FIG. 10: SAPCHB) and to pre-charge the complementary read bit lines in response to the complement sense amplifier pre-charge signal (SAPRB) (see FIG. 10 along with e.g., FIG. 3); and
Jain’s a local control circuit (FIG. 3: 120) does not explicitly disclose claimed sense amplifier pre-charge signal generators.
Desai et al. teach the deficiencies in e.g., FIGS. 1 and 3, and accompanying disclosure, i.e., a local control circuit (see FIG. 3) including:
an internal sense amplifier pre-charge signal generator (300) configured to receive an internal sense amplifier enable signal (SE) and to generate an internal sense amplifier pre-charge signal (SAPRI) (the output node of 330, i.e., internal node of SE) and an inverted version (output node of 330) of the internal sense amplifier pre-charge signal (SAPRI); and
a sense amplifier pre-charge signal (SAPR) generator (300) configured to receive the inverted version of the internal sense amplifier pre-charge signal (SAPRI) (the output node of 330, i.e., internal node of SE), a read signal (READ), and internal clock signal (ICLK) (FIG. 3: rclk, i.e., rclk can be interpreted as an internal clock based on the system clock 205 CLK in FIG. 2) and to generate an inverted version of the complement sense amplifier pre-charge signal (SAPR) (SE) (see FIG. 3 along with FIG. 1, and accompanying disclosure).
Desai et al’ a sense amplifier pre-charge signal generator does not explicitly disclose “a read signal (READ)”.
However, a sense amplifier is a device that performs a read operation. Incorporating a “READ” signal into the sense pre-charge signal is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Lee (US 2005/0232064), FIGS. 2 or 4, precharge signal generator unit input “READ”.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the READ signal for the sense pre-charge circuit because these conventional technology are well established in the art of the memory devices.
Jain and Desai are analogous art because they both are directed to SRAM memory device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jain with the specified features of Desai because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Desai et al. to the teaching of Jain such that a memory, as taught by Jain, utilizes a local control circuit, as taught by Desai et al., for the purpose of generating sense amplifier pre-charge signal related to sense enabling signal, thereby achieving enhanced memory read operations.
Regarding claims 2, 9 and 16, Jain and Desai et al. teach the limitations of claims 1, 8 and 15, respectively.
Jain and Desai further teach the local control circuit further includes a read signal (READ) generator configured to receive the internal sense amplifier pre-charge signal (SAPRI) and the inverted version of the internal sense amplifier pre-charge signal (SAPRI) and to generate a read signal (READ); and the sense amplifier pre-charge signal (SAPR) generator is configured generate the inverted version of the sense amplifier pre-charge signal (SAPR) in response further to the read signal (READ) (see Jain’s FIG. 3: READB signal; and Desai’s FIGS. 1 and 3, and accompanying disclosure, i.e., Desai’s sensing circuit implies claimed a read signal generator).
Regarding claims 3, 10 and 17, Jain and Desai et al. teach the limitations of claims 1, 8 and 15, respectively.
Jain and Desai further teach the sense amplifier and read bit line pre-charger circuit is further configured to receive a sense amplifier enable signal (SAE) and to amplify a voltage difference between the complementary read bit lines in response to the sense amplifier enable signal (SAE) (Jain’s FIG. 3 and Desai’s FIG. 1).
Regarding claims 11 and 18, Jain and Desai et al. teach the limitations of claims 10 and 17, respectively.
Jain further teaches the local control circuit is configured to receive an internal clock signal (ICLK) and to generate an inverted version of the sense amplifier enable signal (SAE) (FIGS. 3-10).
Regarding claims 5, 12 and 19, Jain and Desai et al. teach the limitations of claims 1, 8 and 15, respectively.
Jain further teaches the local I/O circuit further includes complementary bit lines, wherein memory cells of the memory array circuit is connected between the complementary bit lines; and the local I/O circuit is further configured to receive a complement bit line pre-charge signal (BLPCHB) and to pre-charge the complementary bit lines in response to the complement bit line pre-charge signal (BLPCHB) (see FIGS. 3-10 and accompanying disclosure).
Regarding claims 6, 13 and 20, Jain and Desai et al. teach the limitations of claims 1, 8 and 15, respectively.
Jain further teaches the local I/O circuit further includes a read bit line (RBL) transistor and a complement read bit line (RBLB) transistor respectively connected to the complementary read bit lines; and the local I/O circuit is further configured to receive a complement read signal (READB) that activates the read bit line (RBL) transistor and the complement read bit line (RBLB) transistor (see FIGS. 3-10 and accompanying disclosure).
Regarding claims 7 and 14, Jain and Desai et al. teach the limitations of claims 1 and 8, respectively.
Jain further teaches the local I/O circuit further includes: complementary bit lines; a bit line (BL) transistor connected to one of the complementary bit lines; and a complement bit line (BLB) transistor connected to the other of the complementary bit lines; and the local I/O circuit is further configured to receive a column address of the memory array circuit that activates the bit line (BL) transistor and the complement bit line (BLB) transistor (see FIGS. 3-10 and accompanying disclosure).
Regarding claim 21, Jain and Desai et al. teach the limitations of claim 1.
Jain further teaches the read signal (READ) is associated with a read operation of the memory array circuit, and wherein: a falling edge of the complement sense amplifier pre-charge signal (SAPRB) occurs earlier than a falling edge of the read signal (READ); or a falling edge of the complement sense amplifier pre-charge signal (SAPRB) occurs at substantially the same time as a falling edge of the read signal (READ) (see FIG. 10 READB and SAPCHB, and accompanying disclosure).
Response to Argument
Applicant’s amendment filed 04/07/2026, with respect to the rejection(s) of claims under 35 USC 103, have been fully considered but are not persuasive. See the art rejection above for more details. Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825
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