Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the DIV application No. 18/739,600 filed on June 11, 2024.
Information Disclosure Statement
3. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Objections
4. Claims 1, 5-8 are objected to because of the following informalities: In the following, the claims should be recited to avoid indefiniteness due to the phrase of ‘substantially’ which has no definitive measure:
1. (Currently Amended) A semiconductor device, comprising:
a substrate;
a bit line disposed on the substrate and extending along a first direction;
a channel layer connected to the bit line and extending along a second direction
a first word line disposed at a first side of the channel layer, wherein an upper surface of the first word line is
5. (Currently Amended) The semiconductor device of claim 4, wherein an upper surface of the first gate dielectric is
6. (Currently Amended) The semiconductor device of claim 4, wherein an upper surface of the first gate dielectric is
7. (Currently Amended) The semiconductor device of claim 4, wherein a lower surface of the first gate dielectric is
8. (Currently Amended) The semiconductor device of claim 4, wherein a length of the first word line is
Appropriate corrections are needed.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1-7, 9-12 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by IM (US 2023/0122541 A1).
Regarding independent claim 1, IM teaches a semiconductor device (2, para [0037]), comprising (Fig. 2A):
a substrate (101, para [0037]);
a bit line (110, para [0038]) disposed on the substrate (101) and extending along a first direction (x- direction);
a channel layer (120, para [0038]) connected to the bit line (110) and extending along a second direction (z-direction) perpendicular to the first direction; and
a first word line (140a, para [0038]) disposed at a first side of the channel layer (120), wherein an upper surface of the first word line (140a) is aligned with an upper surface of the channel layer (120).
Regarding claim 2, IM teaches wherein (Fig. 2A), further comprising:
a second word line (140b, para [0038]) disposed at a second side of the channel layer (120).
Regarding claim 3, IM teaches wherein (Fig. 2A), the first word line (140a) extends along the second direction (z-direction).
Regarding claim 4, IM teaches wherein (Fig. 2A), further comprising:
a first gate dielectric (130a, para [0038]) disposed between the first word line (140a) and the channel layer (120), wherein the first gate dielectric (130a) extends along the second direction (z-direction).
Regarding claim 5, IM teaches wherein (Fig. 2A), an upper surface of the first gate dielectric (130a) is aligned with (coplanar) the upper surface of the channel layer (120).
Regarding claim 6, IM teaches wherein (Fig. 2A), an upper surface of the first gate dielectric (130a) is aligned with (coplanar) the upper surface of the first word line (140a).
Regarding claim 7, IM teaches wherein (Fig. 2A), a lower surface of the first gate dielectric (130a) is aligned with (coplanar) a lower surface of the first word line (140a).
Regarding claim 9, IM teaches wherein (Fig. 2A), the first gate dielectric (130a) has a bar-shaped profile (see Fig. 2A wherein the gate dielectric 130a shows a vertical rectangular bar-shaped member in the cross-sectional view).
Regarding claim 10, IM teaches wherein (Fig. 2A), the first word line (140a) has a bar-shaped profile (see Fig. 2A wherein the word line 140a shows a vertical rectangular bar-shaped member in the cross-sectional view).
Regarding claim 11, IM teaches wherein (Fig. 2A), the channel layer (120) has a bar-shaped profile (see Fig. 2A wherein the channel 120 shows a vertical rectangular bar-shaped member in the cross-sectional view).
Regarding claim 12, IM teaches wherein (Fig. 2A), a width (horizontal length) of the first word line (140a) is less than a width (horizontal length) of the channel layer (120) along the first direction (x-direction).
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
11. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
12. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over IM (US 2023/0122541 A1) as applied to claim 4 above, and further in view of Jeong et al. (US 2023/0320077 A1).
Regarding claim 8, IM teaches all of the limitations of claim 4 from which this claim depends.
IM is explicitly silent of disclosing wherein, a length of the first word line is the same as a length of the first gate dielectric along a third direction perpendicular to the first direction and the second direction.
Jeong et al. discloses wherein (Fig. 2B), a length of the first word line (34, para [0085]) is the same as a length of the first gate dielectric (32, para [0085]) along a third direction (z-direction) perpendicular to the first direction (x-direction) and the second direction (y-direction).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Jeong et al., and modify the structure of IM by adjusting the length of the word line or the gate dielectric layer, in order to fabricate the cell transistors of memory cells of the DRAM (para [0085]), therefore, simplified the manufacturing process.
13. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over IM (US 2023/0122541 A1) as applied to claim 1 above, and further in view of Sung (US 2023/0164977 A1).
Regarding claim 13, IM teaches all of the limitations of claim 1 from which this claim depends.
IM is explicitly silent of disclosing wherein, further comprising:
a capacitor component on the channel layer.
Sung discloses wherein (Fig. 1D), further comprising:
a capacitor component (130, para [0032]) on the channel layer (121, para [0031]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Sung, and modify the device structure of IM by applying the capacitor structure on the channel layer, in order to fabricate a highly integrated semiconductor device, including memory cells of the DRAM.
Examiner’s Note
14. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
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16. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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