Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the DIV application No. 18/739,600 filed on August 03, 2026.
Information Disclosure Statement
3. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Objections
4. The objections of claims 1, 5-8 have been withdrawn, per the response dated on 08/03/2026.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
8. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
9. Claim 1-7, 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2022/0139918 A1) in view of IM (US 2023/0122541 A1) and further in view of Xiao (US 2024/0064963 A1).
Regarding independent claim 1, Lee teaches a semiconductor device, comprising (Fig. 2E):
a substrate (201, para [0046]);
a bit line (215, para [0046]) disposed on the substrate (201) and extending along a first direction (x-direction);
a cap layer (207 dielectric film, para [0055]) disposed on the bit line (215);
a dielectric pattern (230 ILD, para [0057]) disposed on the cap layer (207);
a channel layer (204) connected to the bit line (215) and extending along a second direction (y-direction) perpendicular to the first direction (x-direction); and
a first word line (212 left) disposed at a first side of the channel layer (204).
wherein the channel layer (204) is extended from a top surface of the bit line (215) and penetrates through the cap layer (207) and the dielectric pattern (230) at a position that a bottom surface of the channel layer (204) is aligned with a bottom surface of the cap layer (207).
Lee is explicitly silent of disclosing wherein, an upper surface of the first word line is aligned with an upper surface of the channel layer; a top surface of the channel layer is aligned with a top surface of the dielectric pattern.
IM discloses wherein (Fig. 2A), an upper surface of the first word line (140a) is aligned with an upper surface of the channel layer (120).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by IM, and modify the structure w/aligned surface of Lee by adjusting the vertical length of the word line and the channel layer, in order to improve the efficiency of current flow in the z-direction through the conductive channels (para [0054]).
Lee and IM are explicitly silent of disclosing wherein, a top surface of the channel layer is aligned with a top surface of the dielectric pattern.
Xiao discloses wherein (Fig. 2), a top surface of the channel layer (1062) is aligned with a top surface of the dielectric pattern (112).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Xiao, and modify the structure w/aligned surface of Lee and IM by adjusting the vertical length of the dielectric pattern and the channel layer, in order to protect side wall of the wordlines structure and the channel layer.
Regarding claim 2, Lee and IM and Xiao teach all of the limitations of claim 1 from which this claim depends.
Lee teaches wherein (Fig. 2E), further comprising:
a second word line (212 right) disposed at a second side (right side) of the channel layer (204);
wherein the first word line (212 left) and the second word line (212 right) are extended through the dielectric pattern (230).
Regarding claim 3, Lee and IM and Xiao teach all of the limitations of claim 1 from which this claim depends.
Lee teaches wherein (Fig. 2E), the first word line (212 left) extends along the second direction (y-direction).
Regarding claim 4, Lee and IM and Xiao teach all of the limitations of claim 1 from which this claim depends.
Lee teaches wherein (Fig. 2E), further comprising:
a first gate dielectric (210) disposed between the first word line (212 left) and the channel layer (204) and disposed on the cap layer (207), wherein the first gate dielectric (210) extends along the second direction (y-direction).
wherein a lower surface of the first gate dielectric (210) is aligned a bottom surface of the dielectric pattern (230) while an upper surface of the first gate dielectric (210) is aligned with the top surface of the dialectic pattern (230 aligned with left portion).
Regarding claim 5, Lee and IM and Xiao teach all of the limitations of claim 4 from which this claim depends.
Lee and IM both disclose wherein (Fig. 2A IM and Fig. 2E Lee), the upper surface of the first gate dielectric (130a) is aligned with the upper surface of the channel layer (120).
Regarding claim 6, Lee and IM and Xiao teach all of the limitations of claim 4 from which this claim depends.
IM discloses wherein (Fig. 2A), the upper surface of the first gate dielectric (130a) is aligned with (coplanar) the upper surface of the first word line (140a).
Regarding claim 7, Lee and IM and Xiao teach all of the limitations of claim 4 from which this claim depends.
IM teaches wherein (Fig. 2A), the lower surface of the first gate dielectric (130a) is aligned with (coplanar) a lower surface of the first word line (140a).
Regarding claim 9, Lee and IM and Xiao teach all of the limitations of claim 4 from which this claim depends.
IM teaches wherein (Fig. 2A), the first gate dielectric (130a) has a bar-shaped profile (see Fig. 2A wherein the gate dielectric 130a shows a vertical rectangular bar-shaped member in the cross-sectional view).
Regarding claim 10, Lee and IM and Xiao teach all of the limitations of claim 1 from which this claim depends.
IM teaches wherein (Fig. 2A), the first word line (140a) has a bar-shaped profile (see Fig. 2A wherein the word line 140a shows a vertical rectangular bar-shaped member in the cross-sectional view).
Regarding claim 11, Lee and IM and Xiao teach all of the limitations of claim 1 from which this claim depends.
IM teaches wherein (Fig. 2A), the channel layer (120) has a bar-shaped profile (see Fig. 2A wherein the channel 120 shows a vertical rectangular bar-shaped member in the cross-sectional view).
Regarding claim 12, Lee and IM and Xiao teach all of the limitations of claim 1 from which this claim depends.
IM teaches wherein (Fig. 2A), a width (horizontal length) of the first word line (140a) is less than a width (horizontal length) of the channel layer (120) along the first direction (x-direction).
Regarding claim 13, Lee and IM and Xiao teach all of the limitations of claim 1 from which this claim depends.
Lee discloses wherein (Fig. 2E), further comprising:
a capacitor component (235, para [0044]) disposed on, overlap on, and in contact with the channel layer (204).
10. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2022/0139918 A1) and IM (US 2023/0122541 A1) and Xiao (US 2024/0064963 A1) as applied to claim 4 above, and further in view of Jeong et al. (US 2023/0320077 A1).
Regarding claim 8, Lee and IM and Xiao teach all of the limitations of claim 4 from which this claim depends.
Lee and IM and Xiao are explicitly silent of disclosing wherein, a length of the first word line is the same as a length of the first gate dielectric along a third direction perpendicular to the first direction and the second direction.
Jeong et al. discloses wherein (Fig. 2B), a length of the first word line (34, para [0085]) is the same as a length of the first gate dielectric (32, para [0085]) along a third direction (z-direction) perpendicular to the first direction (x-direction) and the second direction (y-direction).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Jeong et al., and modify the structure of Lee and IM and Xiao by adjusting the length of the word line or the gate dielectric layer, in order to fabricate the cell transistors of memory cells of the DRAM (para [0085]), therefore, simplified the manufacturing process.
Response to Arguments
11. It has been acknowledged that the applicant amended claims 1-2, 4, 5-8, 13, per the response dated on 08/03/2026.
Applicant’s remarks in pages 5-9 have been considered, but they are moot because of new grounds of rejection in the current office action.
Conclusion
12. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
14. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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