Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-12 are rejected under 35 U.S.C. 102(a1) as being anticipated by Park et al. (US 2023/0402518; hereinafter Park).
Regarding claim 1, Park, in fig. 2, discloses a memory device, comprising: a word line structure 120 disposed in a semiconductor substrate, wherein the word line structure 120 comprises: a lower gate electrode layer 124a; an upper gate electrode layer 124b disposed over and in direct contact with the lower gate electrode layer 124a, wherein a work function of the lower gate electrode layer 124a (metal) is higher than a work function of the upper gate electrode layer 124b (polysilicon) ([0036]); and a gate dielectric layer 122a/122b surrounding the lower gate electrode layer 124a and the upper gate electrode layer 124b; a first source/drain region 114A and a second source/drain region 114B disposed in the semiconductor substrate and at opposite sides of the word line structure 120; a bit line structure 130 disposed over and electrically connected to the first source/drain region 114A; and a capacitor CS1 disposed over and electrically connected to the second source/drain region 114B.
Regarding claim 2, Park discloses wherein the lower gate electrode layer 124a comprises titanium nitride (TiN), and the upper gate electrode layer 124b comprises polysilicon ([0036]).
Regarding claim 3, Park discloses wherein a height of the lower gate electrode layer 124a is greater than a height of the upper gate electrode layer 124b (fig. 2).
Regarding claim 4, Park discloses wherein the lower gate electrode layer 124a is surrounded by a lower portion of the gate dielectric layer 122b, and the upper gate electrode layer 124b is surrounded by an upper portion of the gate dielectric layer 122b, and wherein a thickness of the lower portion of the gate dielectric layer 122b is greater than a thickness of the upper portion of the gate dielectric layer 122b (fig. 2).
Regarding claim 5, Park discloses wherein the word line structure 120 further comprises: a pair of spacers 122c-1 disposed on opposite sides of the upper gate electrode layer 124b, wherein the pair of spacers 122c-1 are sandwiched between the upper portion of the gate dielectric layer 122b and the upper gate electrode layer 124b (fig. 6).
Regarding claim 6, Park discloses wherein the pair of spacers 122c-1 are in direct contact with a top surface of the lower gate electrode layer 124a (fig. 6).
Regarding claim 7, Park discloses further comprising: a dielectric cap layer 126/142 disposed over the semiconductor substrate, wherein a portion of the dielectric cap layer 126 extends into the semiconductor substrate to cover the word line structure 120, and a width of the portion of the dielectric cap layer 126 is greater than a width of the upper gate electrode layer 124b (fig. 6).
Regarding claim 8, Park discloses wherein a width of the lower gate electrode layer 124a is greater than the width of the upper gate electrode layer 124b (fig. 2).
Regarding claim 9, Park discloses wherein the dielectric cap layer 126 is in direct contact with the upper gate electrode layer 124b (fig. 6).
Regarding claim 10, Park discloses further comprising: a lining layer 122c disposed between the gate dielectric layer 122b and the dielectric cap layer 126/142 (fig. 3).
Regarding claim 11, Park discloses wherein a top surface of the lining layer 122c is higher than a top surface of the gate dielectric layer 122a/122b (fig. 2).
Regarding claim 12, Park discloses wherein the upper gate electrode layer 124b is separated from the dielectric cap layer 126/142 by the lining layer 122c (fig. 3).
2. Claims 1, 3, 5-7, 9-12 are rejected under 35 U.S.C. 102(a1) as being anticipated by Lee et al. (US 2017/0365608; hereinafter Lee).
Regarding claim 1, Lee, in fig. 2, discloses a memory device, comprising: a word line structure 132/134 disposed in a semiconductor substrate, wherein the word line structure 132/134 comprises: a lower gate electrode layer 132; an upper gate electrode layer 134 disposed over and in direct contact with the lower gate electrode layer 132, wherein a work function of the lower gate electrode layer 132 is higher than a work function of the upper gate electrode layer 134 ([0056]); and a gate dielectric layer 120 surrounding the lower gate electrode layer 132 and the upper gate electrode layer 134; a first source/drain region 109A and a second source/drain region 109B disposed in the semiconductor substrate and at opposite sides of the word line structure 132/134; a bit line structure 150 disposed over and electrically connected to the first source/drain region 109A; and a capacitor 180 disposed over and electrically connected to the second source/drain region 109B.
Regarding claim 3, Lee discloses wherein a height of the lower gate electrode layer 132 is greater than a height of the upper gate electrode layer 134 (fig. 2).
Regarding claim 5, Lee discloses wherein the word line structure further comprises: a pair of spacers 146 disposed on opposite sides of the upper gate electrode layer 148, wherein the pair of spacers 146 are sandwiched between the upper portion of the gate dielectric layer 120 and the upper gate electrode layer 148 (fig. 2).
Regarding claim 6, Lee discloses wherein the pair of spacers 146 are in direct contact with a top surface of the lower gate electrode layer 132 (fig. 2).
Regarding claim 7, Lee discloses further comprising: a dielectric cap layer 136 disposed over the semiconductor substrate, wherein a portion of the dielectric cap layer 136 extends into the semiconductor substrate to cover the word line structure 132/134, and a width of the portion of the dielectric cap layer 136 is greater than a width of the upper gate electrode layer 134 (fig. 2).
Regarding claim 9, Lee discloses wherein the dielectric cap layer 136 is in direct contact with the upper gate electrode layer 134 (fig. 2).
Regarding claim 10, Lee discloses further comprising: a lining layer 149K disposed between the gate dielectric layer 120 and the dielectric cap layer 136 (figs. 2 & 20B).
Regarding claim 11, Lee discloses wherein a top surface of the lining layer 149K is higher than a top surface of the gate dielectric layer 120 (fig. 20B).
Regarding claim 12, Lee discloses wherein the upper gate electrode layer 134 is separated from the dielectric cap layer 136 by the lining layer 149K (figs. 2 & 20B).
Conclusion
3. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818
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