DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 06/11/2024 Claims 1-10 are pending for this examination.
Oath/Declaration
The oath or declaration filed on 06/11/2024 is acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/29/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-8 provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-8 of co-pending Application No. 18/662,012. This is a provisional double patenting rejection since the conflicting claims have not in fact been patented. Although, the claims at issue are not identical, they are not patentably distinct from each other because of the following:
The following table compares the limitations of the claim/claims of the instant application 18/739,619 and patentably non-distinct claim/claims of the co-pending Application No. 18/662,012.
Instant Application. 18/739,619
Co-pending Application No. 18/662,012
Regarding Claim 1. A semiconductor device, comprising:
a substrate including: a bottom semiconductor layer; a buried insulating layer positioned on the bottom semiconductor layer; and a top semiconductor layer positioned on the buried insulating layer;
a gate structure positioned on the top semiconductor layer; an inner spacer layer positioned on the top semiconductor layer and covering the gate structure; and a plurality of antiferroelectric spacer layers positioned on sides of the inner spacer layer with the gate structure in between and positioned on the top semiconductor layer.
Regarding Claim 1. A semiconductor device, comprising:
a substrate;
a gate structure positioned on the substrate; an inner spacer layer positioned on the substrate and covering the gate structure; and a plurality of antiferroelectric spacer layers positioned on sides of the inner spacer layer with the gate structure in between and positioned on the substrate.
Regarding Claim 2. The semiconductor device of claim 1, wherein the plurality of antiferroelectric spacer layers comprise hafnium and oxygen or zirconium and oxygen
Regarding Claim 2. The semiconductor device of claim 1, wherein the plurality of antiferroelectric spacer layers comprise hafnium and oxygen or zirconium and oxygen.
Regarding Claim 3. The semiconductor device of claim 1, wherein the plurality of antiferroelectric spacer layers are crystalline.
Regarding Claim 3. The semiconductor device of claim 1, wherein the plurality of antiferroelectric spacer layers are crystalline.
Regarding Claim 4. The semiconductor device of claim 1, wherein the plurality of antiferroelectric spacer layers are tetragonal.
Regarding Claim 4. The semiconductor device of claim 1, wherein the plurality of antiferroelectric spacer layers are tetragonal.
Regarding Claim 5. The semiconductor device of claim 1, wherein the plurality of antiferroelectric spacer layers comprise dopants.
Regarding Claim 5. The semiconductor device of claim 1, wherein the plurality of antiferroelectric spacer layers comprise dopants.
Regarding Claim 6. The semiconductor device of claim 5, wherein the dopants comprise silicon, aluminum, germanium, magnesium, calcium, strontium, barium, or titanium.
Regarding Claim 7. The semiconductor device of claim 1, further comprising a plurality of recesses recessed from a top surface of the top semiconductor layer, adjacent to the gate structure, defining a channel region between the plurality of recesses and under the gate structure.
Regarding Claim 6, The semiconductor device of claim 5, wherein the dopants comprise silicon, aluminum, germanium, magnesium, calcium, strontium, barium, or titanium.
Regarding Claim 7. The semiconductor device of claim 1, further comprising a plurality of recesses recessed from a top surface of the substrate, adjacent to the gate structure, defining a channel region between the plurality of recesses and under the gate structure.
Regarding Claim 8. The semiconductor device of claim 7, further comprising a plurality of impurity regions comprising: a plurality of lightly doped portions positioned within the top semiconductor layer and separated from each other with the channel region in between; and a plurality of bulk doped portions positioned within the top semiconductor layer, respectively connected to the plurality of lightly doped portions.
Regarding Claim 8, The semiconductor device of claim 7, further comprising a plurality of impurity regions comprising: a plurality of lightly doped portions positioned within the substrate and separated from each other with the channel region in between; and a plurality of bulk doped portions positioned within the substrate, respectively connected to the plurality of lightly doped portions.
As demonstrated, for example the combination of independent claim Instant Application. 18/739,619 discloses the features of the independent claims 1-8 of Co-pending Application No. 18/662,012, while the claims are broader in scope and anticipate the claimed invention in the parent.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 2014/0117467 A1; hereafter Yang) in view of KAVALIEROS et al (US 2020/0312978 A1; hereafter KAVALIEROS).
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Regarding claim 1. Yang discloses a semiconductor device, comprising:
a substrate (Fig 1, substrate 102, Para [ 0008-0009]) including: a bottom semiconductor layer (Fig 1, silicon on insulator substrate 102, Para [ 0008-0009]); a buried insulating layer positioned on the bottom semiconductor layer (Fig 1, silicon on insulator substrate 102, Para [ 0008-0009]); and a top semiconductor layer (Fig 1, silicon on insulator substrate 102, Para [ 0008-0009]) positioned on the buried insulating layer (Fig 1, silicon on insulator substrate 102, Para [ 0008-0009], it is evidence by Fogel et al 2015/0303281, as discloses in Para [ 0031], “semiconductor substrate 5 is a semiconductor on insulator (SOI) substrate that includes a bottom semiconductor layer 1 and a top semiconductor layer 3 (which is interchangeably referred to as a semiconductor on insulator (SOI) layer 3) that are electrically isolated from each other by a buried insulating layer 2.”);
a gate structure (gate structure [ 112,110], construed as gate structure, Para [ 0008]) positioned on the top semiconductor layer (Fig 1, substrate 102, Para [ 0008]);
an inner spacer layer (Fig 1, “inner spacer 118 can cover the gate electrode 110 completely”, Para [ 0012]) positioned on the substrate (Fig 1, substrate 102, Para [ 0008]) and covering the gate structure (inner spacer 118, Para [ 0012]); and
a plurality of spacer layers (Fig 1, spacers [116], Para [ 0012-0013]) positioned on sides of the inner spacer layer (inner spacer 118, Para [ 0012]) with the gate structure (gate structure [ 112,110], Para [ 0008]) in between and positioned on the substrate (Fig 1, substrate 102, Para [ 0008]).
But Yang does not disclose explicitly antiferroelectric spacer layers.
In a similar field of endeavor, KAVALIEROS discloses antiferroelectric spacer layers (Para [ 0042-0043]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang in light of KAVALIEROS teaching “antiferroelectric spacer layers (Para [ 0042-0043])” for further advantage such as providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material.
Regarding claim 2. Yang and KAVALIEROS disclose the semiconductor device of claim 1, KAVALIEROS further disclose wherein the plurality of antiferroelectric spacer layers comprise hafnium and oxygen or zirconium and oxygen (Para [ 0042-0043]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang in light of KAVALIEROS teaching “wherein the plurality of antiferroelectric spacer layers comprise hafnium and oxygen or zirconium and oxygen (Para [ 0042-0043])” for further advantage such as providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material.
Regarding claim 5. Yang and KAVALIEROS disclose the semiconductor device of claim 1, KAVALIEROS further disclose wherein the plurality of antiferroelectric spacer layers comprise dopants (Para [ 0042-0043]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang in light of KAVALIEROS teaching “wherein the plurality of antiferroelectric spacer layers comprise dopants (Para [ 0042-0043])” for further advantage such as providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material.
Regarding claim 6. Yang and KAVALIEROS disclose the semiconductor device of claim 5, KAVALIEROS further disclose wherein the dopants comprise silicon, aluminum, germanium, magnesium, calcium, strontium, barium, or titanium (Para [ 0042-0043]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang in light of KAVALIEROS teaching “wherein the dopants comprise silicon, aluminum, germanium, magnesium, calcium, strontium, barium, or titanium (Para [ 0042-0043])” for further advantage such as providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 2014/0117467 A1; hereafter Yang) in view of KAVALIEROS et al (US 2020/0312978 A1; hereafter KAVALIEROS) as applied claims above and further in view of SHARANGPANI et al (US 2021/0050371 A1; hereafter SHARANGPANI).
Regarding claim 3. Yang and KAVALIEROS disclose the semiconductor device of claim 1, KAVALIEROS further disclose plurality of antiferroelectric spacer layers comprise hafnium and oxygen or zirconium and oxygen (Para [ 0042-0043], which is same material discloses instant application).
But Yang and KAVALIEROS does not disclose explicitly spacer layers are crystalline.
In a similar field of endeavor, SHARANGPANI discloses spacer layers are crystalline (Para [ 0093]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang and KAVALIEROS in light of SHARANGPANI teaching “wherein the plurality of antiferroelectric spacer layers are crystalline (Para [ 0093])” for further advantage such as enables stable integration process with a spacer structure which comprises an (anti)ferromagnetic material.
Regarding claim 4. Yang and KAVALIEROS disclose the semiconductor device of claim 1, KAVALIEROS further disclose plurality of antiferroelectric spacer layers comprise hafnium and oxygen or zirconium and oxygen (Para [ 0042-0043], which is same material discloses instant application)
But Yang and KAVALIEROS does not disclose explicitly spacer layers are tetragonal.
In a similar field of endeavor, SHARANGPANI discloses spacer layers are crystalline (Para [ 0093]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang and KAVALIEROS in light of SHARANGPANI teaching “spacer layers are crystalline (Para [ 0093])” for further advantage such as enables stable integration process with a spacer structure which comprises an (anti)ferromagnetic material.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 2014/0117467 A1; hereafter Yang) in view of KAVALIEROS et al (US 2020/0312978 A1; hereafter KAVALIEROS) as applied claims above and further in view of Qin et al (US 2013/0316509 A1; hereafter Qin).
Regarding claim 7. Yang and KAVALIEROS disclose the semiconductor device of claim 1, Yang further discloses plurality of source/drain regions (source/drain regions 10, Para [ 0008]) from a top surface of the substrate ( substrate 102, Para [ 0008]), adjacent to the gate structure (gate structure [ 112,110], construed as gate structure, Para [ 0008]), defining a channel region ( between source/drain region 106, Para [ 0008]) between the plurality of source/drain regions (source/drain regions 10, Para [ 0008]) and under the gate structure (gate structure [ 112,110], construed as gate structure, Para [ 0008]).
But Yang and KAVALIEROS does not disclose explicitly further comprising a plurality of recesses recessed from a top surface of the substrate, adjacent to the gate structure, defining a channel region between the plurality of recesses and under the gate structure.
In a similar field of endeavor, Qin discloses a plurality of recesses recessed from a top surface of the substrate (Fig 1-2, plurality recess 15 formed top of the SOI substrate 10 and form source/drain region 17, Para [ 0032, 0039]), adjacent to the gate structure (Fig 2-4, Para [ 0032-0039]), defining a channel region between the plurality of recesses and under the gate structure (Fig 2-4, Para [ 0032-0039]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang and KAVALIEROS in light of Qin teaching “a plurality of recesses recessed from a top surface of the substrate (Fig 1-2, plurality recess 15 formed top of the SOI substrate 10 and form source/drain region 17, Para [ 0032, 0039]), adjacent to the gate structure (Fig 2-4, Para [ 0032-0039]), defining a channel region between the plurality of recesses and under the gate structure (Fig 2-4, Para [ 0032-0039])” for further advantage such as effectively improve the performances of the transistor.
Regarding claim 8. Yang and KAVALIEROS in light of Qin discloses the semiconductor device of claim 7, Yang further discloses further comprising a plurality of impurity regions comprising:
a plurality of lightly doped portions (Fig 7, lightly doped regions 108, Para [ 0010]) positioned within the substrate (substrate 102, Para [ 0002]) and separated from each other with the channel region in between ( between source/drain region 106, Para [ 0008]); and a plurality of bulk doped portions (source/drain 106, Para [ 0010]) positioned within the substrate (substrate 102, Para [ 0008]), respectively connected to the plurality of lightly doped portions (Fig 7, lightly doped regions 108, Para [ 0010]).
Regarding claim 9. Yang and KAVALIEROS in light of Qin discloses the semiconductor device of claim 8 Yang further discloses, further comprising an outer spacer layer (outer spacer 120, Para [ 0008]) positioned on the plurality of bulk doped portions (source/drain 106, Para [ 0010]) and covering the plurality of spacer layers (Fig 1, spacers [116], Para [ 0012-0013]) and the inner spacer layer (inner spacer 118, Para [ 0012]).
But Yang does not disclose explicitly antiferroelectric spacer layers.
In a similar field of endeavor, KAVALIEROS discloses antiferroelectric spacer layers (Para [ 0042-0043]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang in light of KAVALIEROS teaching “antiferroelectric spacer layers (Para [ 0042-0043])” for further advantage such as providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 2014/0117467 A1; hereafter Yang) in view of KAVALIEROS et al (US 2020/0312978 A1; hereafter KAVALIEROS) and Qin et al (US 2013/0316509 A1; hereafter Qin) as applied claims above and further in view of LU et al (US 2023/0402457 A1; hereafter LU).
Regarding claim 10. Yang and KAVALIEROS in light of Qin disclose the semiconductor device of claim 8, But Yang, KAVALIEROS and Qin does not disclose explicitly wherein a ratio of a thickness of the gate structure to a maximal depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions is between about 7.00 and about 3.60.
In a similar field of endeavor, LU discloses wherein a ratio of a thickness of the gate structure to a maximal depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions is between about 7.00 and about 3.60 (Fig 2, Para [ 0099] discloses “upper conductive portion 212U of the gate region 212 has a vertical thickness TV about 10 nm to 15 nm” and Para [ 0111] discloses “the lower conductive portion 212L of the gate region 212 is around 2 nm to 4 nm or less” and “a vertical thickness of the N type LDD region is less than 20 nm, Para [ 0017]. Based on the combine gate region thickness and LDD thickness less 20 nm, maximal depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions desired ratio can be achieved. Examiner interpreted LDD region is less than 20 nm, can be any range less than 20 nm, which can be applied for the claim limitation).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang, KAVALIEROS and Qin in light of LU teaching “a plurality of recesses recessed from a top surface of the substrate, adjacent to the gate structure (Fig 2-4, Para [ 0030-0034]), defining a channel region between the plurality of recesses and under the gate structure (Fig 2-4, Para [ 0030-0034])” for further advantage such as minimizes current leakages, increases channel-conduction performance and control, and optimizes functions of source and drain regions.
Examiner like to note that, applicant has not presented persuasive evidence that the claimed “wherein a ratio of a thickness of the gate structure to a maximal depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions is between about 7.00 and about 3.60” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed ratio). Also, the applicant has not shown that the claimed ratio 7.00 and about 3.60 produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
It has been held that it is a prima facie obvious by change of size in view of In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), see MPEP 2144.04.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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