DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 8-10 are allowed.
Claim 13-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 8 includes allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: a memory testing device configured to perform at least one memory test on a memory block of a memory; and a processor coupled to the memory testing device, wherein the processor is configured to extract, from the at least one memory test, a location of at least one fail bit to be repaired in the memory block, obtain an available repair resource in the memory for repairing the memory block, determine, using first machine learning, whether the at least one fail bit is unrepairable according to the location of the at least one fail bit in the memory block, and the available repair resource, and in response to determining, using the first machine learning, that the at least one fail bit is not unrepairable, determine whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable, the plurality of constraints corresponding to the location of the at least one fail bit in the memory block, and the available repair resource, in response to determining that the CSP is not solvable, control the memory testing device to mark the memory block as unrepairable or to reject the memory, and in response to determining that the CSP is solvable, update a heuristic of the CSP using second machine learning separate from the first machine learning., and a combination of other limitations in the independent claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujii (PGPUB 20100169705), hereinafter as Fujii, in view of Shimada (Patent 6112321), hereinafter as Shimada.
Regarding claim 1, Fujii teaches a method, said method executed at least partially by a processor, comprising:
extracting, from at least one memory test on a memory block of a memory (Fig 1, memory test apparatus), a location of at least one fail bit to be repaired in the memory block (Fig 3);
obtaining an available repair resource in the memory for repairing the memory block (Fig 8, S500 allocating backup lines);
checking, using machine learning (argument used in office action dated 4/5/2022 for application 17108870 [now US Patent 11450401] applies), whether the at least one fail bit is unrepairable according to the location of the at least one fail bit in the memory block, and the available repair resource (Fig 7);
in response to said checking, using the machine learning, indicating that the at least one fail bit is not unrepairable (Fig 7 and Fig 8, see above Response to Arguments), determining whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable (Fig 8, S502-504, weight coefficient, available backup lines), the plurality of constraints corresponding to the location of the at least one fail bit in the memory block, and the available repair resource (Fig 8, S516);
in response to said determining indicating that the CSP is not solvable, marking the memory block as unrepairable or rejecting the memory (Fig 7 and Fig 8).
But not expressly marking the memory block as unrepairable or rejecting the memory without making further determination with respect to repairability of the memory block,
Shimada teaches marking the memory block as unrepairable or rejecting the memory without making further determination with respect to repairability of the memory block (Fig 2 and col 4 line 41-43).
Since Shimada and Fujii are both from the same field of semiconductor memory device, the purpose disclosed by Shimada would have been recognized in the pertinent art of Fujii.
It would have been obvious at the time the invention was filed to a person having ordinary skill in the art to stop the testing/repairing when it is not repairable as in Shimada into the device/method of Fujii for the purpose of shortening the testing/repairing process.
Regarding claim 2, Fujii teaches the CSP further contains at least one objective function to be optimized, and the solution of the CSP corresponds to the at least one objective function being optimized (Fig 8, looping with updating weighting coefficient).
Regarding claim 12, Shimada teaches in response to determining that the at least one fail bit is unrepairable, control the memory testing device to mark the memory block as unrepairable or to reject the memory, without performing a memory test on the memory block to extract a location of a weak bit in the memory block (Fig 2 and col 4 line 41-43).
Claim(s) 5-6, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fuji and Shimada, in view of Kim et al. (PGPUB 20130262740), hereinafter as Kim.
Regarding claim 5, Fujii and Shimada teach a method as in rejection of claim 1,
And also extracting, from the at least one memory test, a location of at least one weak bit in the memory block (Fig 3, fail data locations);
in response to said determining indicating that the CSP is solvable, determining whether a remaining repair resource exists based on the available repair resource and the solution of the CSP (Fig 8, looping with S502);
in response to a determination that the remaining repair resource exists, solving a Constraint Optimization Problem (COP) containing the plurality of constraints, and an objective function (Fig 8, S504) to be optimized, the objective function corresponding to the location of the at least one weak bit in the memory block;
But not expressly repairing the at least one weak bit using the available repair resource in accordance with a solution of the COP;
Kim teaches repairing the at least one fail bit and the at least one weak bit using the available repair resource in accordance with a solution of the COP ([0084]).
Since Kim and Fujii are both from the same field of semiconductor memory device, the purpose disclosed by Kim would have been recognized in the pertinent art of Fujii.
It would have been obvious at the time the invention was filed to a person having ordinary skill in the art to repair weak cell as in Kim into the device/method of Fujii for the purpose of improving memory device performance.
Regarding claim 6, Fujii teaches assigning a plurality of different weights to the plurality of weak bits, the different weights corresponding to different weakness levels of the plurality of weak bits (Fig 3, assigning weighting coefficients on failed cells).
Regarding claim 18, Fujii teaches to assign a plurality of different weights to the plurality of weak bits, the different weights corresponding to different weakness levels of the plurality of weak bits, and based on locations of and the plurality of different weights assigned to the plurality of weak bits, control a repair of the at least one fail bit and one or more weak bits among the plurality of weak bits (Fig 3 and Fig 7).
Regarding claim 19, Fujii teaches to assign, among the plurality of different weights, at least one weight, which corresponds to a weakness level of the at least one first weak bit in the available repair resource in the memory, to the at least one first weak bit in the available repair resource in the memory, and based on the locations of and the plurality of different weights assigned to the plurality of weak bits including the at least one first weak bit in the available repair resource, control the repair of the at least one fail bit and the one or more weak bits among the plurality of weak bits (Fig 3).
Regarding claim 20, Fujii teaches to control the repair of the at least one fail bit and the one or more weak bits among the plurality of weak bits, by allocating, from the available repair resource, a redundant bit line or word line not including the at least one first weak bit to the repair, before allocating a redundant bit line or word line including the at least one first weak bit (Fig 7).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fuji.
Regarding claim 11, Fujii teaches a computer program product, comprising a non-transitory, computer-readable medium containing instructions therein which, when executed by a processor, cause the processor to
extract a location (Fig 3) of at least one fail bit to be repaired in a memory block of a memory,
obtain an available repair resource (Fig 8) in the memory for repairing the memory block,
determine whether the at least one fail bit is repairable according to the location of the at least one fail bit in the memory block, and the available repair resource (Fig 8, S500-502),
in response to determining that the at least one fail bit is repairable, determine whether a remaining repair resource exists upon allocating at least a part of the available repair resource to repair the at least one fail bit (Fig 7), and
in response to determining that the remaining repair resource exists, control a memory testing device to perform at least one memory test on the memory block to extract a location of at least one weak bit in the memory block (Fig 3).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim 1-7, 11-12, 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 12014790.
Claim 1-7, 11-12, 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 11450401, in view of teaching of Shimada.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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/MIN HUANG/Primary Examiner, Art Unit 2827