Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Currently, claims 1-20 are pending and examined below.
Information Disclosure Statement (IDS)
The information disclosure statement submitted on 06/11/2024 ("06-11-24 IDS") is in compliance with the provisions of 37 CFR 1.97. Accordingly, the 06-11-24 IDS is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE HAVING HYBRID DIELECTRIC BAR CONTACTING BACKSIDE BEOL STRUCTURE
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4-6, 8, 10 and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pub. No. US 2024/0250032 A1 to Chiang et al. ("Chiang").
Figs. 31A and 31B of Chiang have been provided to support the rejection below:
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Regarding independent claim 1, Chiang teaches a semiconductor device (see Figs. 31A and 31B, for example) comprising:
a hybrid dielectric bar 90, 172 (para [0033] - “The insulation material 74 may be an oxide, such as silicon oxide”; para [0046] - “In FIGS. 12A-12B, the insulation material 74 is recessed to form isolation regions 90, e.g., shallow trench isolation (STI) regions.”; para [0091] - “The ESL 172 may be formed of a dielectric material having a high etching selectivity to the dielectric material of the fourth ILD 174, such as silicon nitride…”) present between a first transistor 50N (para [0020] - “The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type nanostructure-FETs, and the p-type region 50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type nanostructure-FETs.”) of a first conductivity type (n-type) and a second transistor 50P of a second conductivity type (p-type) that is different from the first conductivity type, wherein the hybrid dielectric bar 90, 172 comprises an upper portion 90 (e.g., silicon oxide) composed of a first dielectric structure 90 having a first dielectric constant and a lower portion 172 composed of a second dielectric structure 172 having a second dielectric constant (e.g., silicon nitride), wherein the second dielectric constant is greater than the first dielectric constant (Silicon nitride has a higher dielectric constant than silicon oxide.); and
a backside back-end-of-the-line (BEOL) structure 180 (para [0093] - “The back-side interconnect structure 180 is referred to as a back-side interconnect structure because it is formed at the back-side of the device layer 140.”) electrically connected to a first device source/drain region 82L and/or 84L (para [0087] - “lower LDD regions 82L”; para [0016] - “lower source/drain regions 84L”) of the first transistor 50N and to a second device source/drain region 82L and/or 84L (para [0087] - “lower LDD regions 82L”; para [0016] - “lower source/drain regions 84L”) of the second transistor 50P, wherein the hybrid dielectric bar 90, 174 contacts the backside BEOL structure 180.
Regarding claim 2, Chiang teaches a frontside BEOL structure 150 (para [0078] - “a front-side interconnect structure 150”) electrically connected to both the first transistor 50N and the second transistor 50P.
Regarding claim 4, Chiang teaches the first transistor 50N and the second transistor 50P that share a common gate structure 104, 102 and/or 118 (para [0057] - “gate electrodes 104…a gate contact 118.”; para [0063] - “gate dielectrics 102”).
Regarding claim 5, Chiang teaches the common gate structure 104, 102 and/or 118 that extends over a topmost surface of the hybrid dielectric bar 90, 172.
Regarding claim 6, Chiang teaches the lower portion of the hybrid dielectric bar 90, 172 separates a VSS backside power rail from a VDD backside power rail (para [0096] - “Some or all of the conductive features 184 are power rails 184P, which are conductive lines that electrically connect the lower source/drain regions 84L to a reference voltage, supply voltage, or the like, through the lower source/drain vias 178.”) (Fig. 31A shows two separate power rails 184P, 184P. More likely than not, they cannot be at the same voltage so one would be at a reference voltage and the other at the supply voltage.).
Regarding claim 8, Chiang teaches the lower portion of the hybrid dielectric bar separates a VSS backside contact conductor material layer from a VDD backside contact conductor material layer.
Regarding claim 10, Chiang teaches a gate cut pillar 72 or 104 (para [0094] - “gate spacers 72”; para [0097] - “gate electrode 104”) located adjacent to the first transistor 50N wherein the gate cut pillar 72 or 104 has a topmost surface that is vertically offset and is located above a topmost surface of the hybrid dielectric bar 90, 172.
Regarding claim 11, Chiang teaches the gate cut pillar 72 (para [0029] - “The gate spacers 72 can then be formed by conformally forming an insulating material in the sidewall recesses and the trenches 68, and subsequently etching the insulating material. The insulating material may be silicon nitride, silicon carbonitride, silicon oxycarbide, or silicon oxycarbonitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized.”) that is composed entirely of the first dielectric structure.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 is objected to for depending on a rejected base claim 1 but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 3.
Claim 7 is objected to for depending on a rejected base claim 1 and the intervening claim 6 but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 and the intervening claim 6 or the base claim 1 is amended to include all of the limitations of claim 7 and the intervening
claim 7.
Claim 9 is objected to for depending on a rejected base claim 1 and the intervening claim 8 but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 and the intervening claim 8 or the base claim 1 is amended to include all of the limitations of claim 9 and the intervening
claim 8.
Regarding independent claim 12, Chiang teaches a semiconductor device (see Fig. 1; see also Figs. 31A and 31B; para [0018] - “FIGS. 2A-31B are views of intermediate stages in the manufacturing of nanostructure-FETs, in accordance with some embodiments. FIGS. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28A, 29A, 30A, and 31A illustrate cross-sectional views along a similar cross-section as reference cross-section A-A′ in FIG. 1. FIGS. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B, 23B, 24B, 25B, 26B, 27B, 28B, 29B, 30B, and 31B illustrate cross-sectional views along a similar cross-section as reference cross-section B-B′ in FIG. 1.”) comprising:
a first active device area comprising a first set of first transistors 50N (along B-B’) of a first conductivity type (n-type);
a second active device area located adjacent to the first active device 50N and comprising a second set of first transistors 50N (along B-B’) of the first conductivity type;
a third active device area located adjacent to the second active device area and comprising a first set of second transistors 50P (along A-A’) of a second conductivity type (p-type) that is different from the first conductivity type;
a fourth active device area located adjacent to the third active device area and comprising a second set of second transistors 50P (along A-A’) of the second conductivity type;
Nevertheless, the independent claim 12 is allowed, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 12, a hybrid dielectric bar present between the second set of first transistors and the first set of second transistors, wherein the hybrid dielectric bar comprises an upper portion composed of a first dielectric structure having a first dielectric constant and a lower portion composed of a second dielectric structure having a second dielectric constant, wherein the second dielectric constant is greater than the first dielectric constant;
a first gate cut pillar located between the first set of first transistors and the second set of first transistors; and
a second gate cut pillar located between the first set of second transistors and the second set of second transistors, wherein the first gate cut pillar and the second gate cut pillar are composed entirely of the first dielectric structure.
Claims 13-20 are allowed, because they depend from the allowed independent claim 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2025/0218901 A1 to Senaratne et al.
Pub. No. US 2023/0067715 A1 to Yuh et al.
Pub. No. US 2022/0302268 A1 to Chiang et al.
Pub. No. US 2021/0336019 A1 to Su et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 23 September 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status
