DETAILED ACTION
This is the Office action based on the 18740482 application filed June 11, 2024, and in response to applicant’s argument/remark filed on June 3, 2026. Claims 1-16 are currently pending and have been considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Interpretations
Claim 1 recites “A method for planarizing a surface of a semiconductor device, comprising:
providing a substrate, wherein a component is disposed on the substrate;
forming a first dielectric layer to cover the component, wherein the first dielectric layer comprises a protruding portion corresponding to the component;
etching a portion of the protruding portion to form a sidewall structure;
forming a second dielectric layer to cover the first dielectric layer, wherein a hardness of the second dielectric layer is greater than a hardness of the first
dielectric layer; and
completely removing the second dielectric layer and the sidewall structure, such that the first dielectric layer is planarized.” (emphases added)--Since claim 1 does not recite how the sidewall structure is formed, i.e. whether the sidewall structure is formed by a deposition, such as polymer, on a sidewall during the etching; or whether the sidewall structure is a structure that has a sidewall that is a remnant of the component, or of the protruding portion, or of an undisclosed component,… Therefore, for the purpose of examining it will be assumed that the sidewall structure is any structure that has a sidewall that is formed as a result of the etching.
--Since claim 1 does not specify which portion of the first dielectric layer is planarized, for the purpose of examining it will be assumed that any portion, e.g. top, bottom or sidewall, of the first dielectric layer is planarized.--Since the step of “etching a portion of the protruding portion to form a sidewall structure” and the step of “forming a second dielectric layer to cover the first dielectric layer” are independent from each other; therefore, either step may be performed prior to the other step.
Claim Rejections - 35 USC § 102/35 USC § 103
The following is a quotation of 35 U.S.C. 102:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention..
The following is a quotation of 35 U.S.C. 103:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6 and 13-16 rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Sung et al. (U.S. PGPub. No. 20150228754), hereinafter “Sung”:--Claim 1: Sung teaches a method for fabricating a semiconductor device (abstract), comprisingforming a protrusion on a substrate (Fig. 3A);
forming a first dielectric layer 52A over the protrusion (Fig. 3B), the first layer 52A may be made of silicon oxide ([0063]);forming a second dielectric layer 53 over the first dielectric layer 52A (Fig. 3B, 3C), the second dielectric layer 53A may be made of TiN ([0064-0066]);perform a first etching to remove a top portion of the first dielectric layer 52A to form a sidewall structure 52, which is the portion of the first dielectric layer 52A on the sidewall of the protrusion (Fig. 3F and 3G, [0074-0078]);perform a second etching to completely remove the second dielectric layer 53 and a portion of the first dielectric layer 52A (Fig. 3I, [0077-0080]). It is noted that TiN has a higher Moh harness, 9, than silicon oxide, 7. It is also noted that the remainder of the first dielectric layer 52A (Label 52R) is planarized (Fig. 3I) Alternately, although Sung does not disclose that the second etching of the sidewall structure is performed such that the first dielectric layer is planarized, since Fig. 3I shows that the remainder of the first dielectric layer 52A (Label 52R) is planarized, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to perform the second etching such that the first dielectric layer is planarized.--Claims 2, 3, 4: Fig. 3G shows that the etching the portion of the protruding portion forms a recess, and the sidewall structure is adjacent to the recess, wherein the sidewall structure comprise a vertical surface facing the recess, and wherein the recess overlaps the component in a vertical direction.--Claims 5, 6: Sung further teaches that the first etching comprises forming a mask 58 over the protrusion ([0077]), and performing a dry etch to recess the first dielectric layer 52A ([0078]).--Claim 13: Sung further teaches that the semiconductor device may be a FeRAM device ([0086]) and that the protrusion comprises a high dielectric gate dielectric layer ([0032, 0058]). It is noted that a high dielectric gate dielectric layer is capable of being a magnetic tunnel junction component.--Claim 14, 15: Sun further teaches that the height of the second dielectric layer 53 is controlled to be lower than the upper surface of a gate structure and higher than an upper portion of a second gate electrode ([0066]). Sung further teaches that the first etching comprises a CMP to recess the first dielectric layer 52 that is controlled so that the second dielectric layer 53 is not exposed ([0075]), and a dry etch or a wet etch that further recesses the first dielectric layer 52 ([0078]). Therefore, the height and a thickness of the sidewall structure are result-effective variables, and it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to perform the first etching so that the height and thickness of the sidewall structure are within the claimed ranges because "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”. MPEP 2144.05(II)(A).--Claim 16: Sung further teaches that the second dielectric layer 53 may be formed to a thickness of 100 A ([0064]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 6, and 14-16 rejected under 35 U.S.C. 103 as obvious over Tseng et al. (U.S. PGPub. No. 20160307769), hereinafter “Tseng”:--Claim 1: Tseng teaches a method of processing a semiconductor device, comprising:forming a protrusion 306 on a substrate, wherein the protrusion 306 may be made of amorphous silicon (Fig. 5, [0025]);forming a first dielectric layer 602 that covers that protrusion (Fig. 6A, [0029]);selectively removing a top portion of the first dielectric layer 602 to form a sidewall structure (Fig. 6B, [0030]);forming a second dielectric layer 802 over the first dielectric layer 602, wherein the second dielectric layer 802 may be made of semiconductor nitride (Fig. 8, [0032]);selectively and completely removing the second dielectric layer 802 (Fig. 10, [0034]), and removing a portion of the first dielectric layer 602 (Fig. 16, [0040]). Tseng further teaches that the first dielectric layer 602 may be formed of a material that has a different etchant selectivity to the layer 306. In one example Tseng teaches that silicon oxide, silicon nitride and amorphous silicon have different etch selectivity with respect to each other ([0029]). Therefore, since Tseng teaches that the selectively removing a top portion of the first dielectric layer 602 is with respect to the protrusion 306, and that the selectively removing the second dielectric layer 802 is with respect to the first dielectric layer 602, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to form the first dielectric layer 602 from silicon oxide, and the second dielectric layer 802 from silicon nitride. It is noted that silicon nitride has a higher Vickers hardness, 14, than silicon oxide, 7. It is noted that the remaining portion of the first dielectric layer 602 comprises a plurality of sections that have the same top level (Fig. 16 and 17); therefore, the first dielectric layer is planarized. Alternately, although Tseng does not disclose that the first dielectric layer is planarized, since Fig. 16 and 17 show the remaining portion of the first dielectric layer 602 consisting of a plurality of sections that have the same top level, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to perform the completely removing such that the remaining portion of the first dielectric layer 602 consisting of a plurality of sections that have the same top level, thus is planarized.--Claims 2, 3, 4: Fig. 6B shows that the first etching forms a recess adjacent to a sidewall structure, wherein the sidewall structure comprises a vertical surface facing the recess and wherein the recess overlaps the protrusion in a vertical direction.--Claim 6: Tseng further teaches that the first etching may be a dry etching ([0030]).--Claims 14, 15, 16: Tseng further teaches that the method enables fabrication device features having smaller critical dimensions ([0003]), and that the method may be used for a features having a variety of shapes, thicknesses, pitches and widths ([0027, 0030]). Therefore, the height and a thickness of the sidewall structure are result-effective variables, and it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to perform the first etching so that the height and thickness of the sidewall structure are within the claimed ranges because "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”. MPEP 2144.05(II)(A).
Allowable Subject Matter
Claims 7-12 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 7, none of the cited prior arts teaches the feature “the second dielectric layer and the sidewall structure are completely removed by a chemical mechanical polishing process” in the context of claim 7;with respect to claim 10, none of the cited prior arts teaches the feature “a ratio of the hardness of the second dielectric layer to the hardness of the first dielectric layer ranges from 4 to 6” in the context of claim 10;
with respect to claim 11, none of the cited prior arts teaches the feature “the first dielectric layer comprises a porous dielectric material” in the context of claim 11;with respect to claim 12, none of the cited prior arts teaches the feature “the second dielectric layer comprises tetraethoxysilane” in the context of claim 12.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submission should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Response to Arguments
Applicant's arguments filed June 3, 2026 have been fully considered as follows:--Regarding Applicant’s argument that the amendments to the claims have overcome the rejections of claims 10 and 11 under 35 U.S.C. 112 (b), this argument is persuasive. These rejections are withdrawn.--Regarding Applicant’s argument that the previously cited prior arts do not teach the amended features, this arguments is persuasive. It is noted that claim 1 has been amended to have a different scope. New grounds of rejection based on newly found prior arts are shown above.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP §706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS PHAM whose telephone number is (571) 270-7670 and fax number is (571) 270-8670. The examiner can normally be reached on MTWThF9to6 PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached on (571) 270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS T PHAM/Primary Examiner, Art Unit 1713
Prosecution Insights