Prosecution Insights
Last updated: August 18, 2026
Application No. 18/740,496

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §112
Filed
Jun 11, 2024
Priority
Aug 27, 2021 — CN 202110993723.6 +1 more
Examiner
CHI, SUBERR L
Art Unit
Tech Center
Assignee
United Microelectronics Corp.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
551 granted / 653 resolved
+24.4% vs TC avg
Minimal +3% lift
Without
With
+2.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
25 currently pending
Career history
669
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
44.6%
+4.6% vs TC avg
§102
23.7%
-16.3% vs TC avg
§112
28.4%
-11.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 653 resolved cases

Office Action

§112
DETAILED ACTION Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election Applicant’s election of claims #9-17 in the reply filed on July 6, 2026 is acknowledged. Because the Applicant did not distinctly and specifically point out errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)). IDS The IDS document(s) filed on June 11, 2024 and October 17, 2025 and December 3, 2025 and March 4, 2026 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action. Specifications The title is objected to because a more descriptive title is requested. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: reference number 14 in FIG. 1 and other drawings. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections – 35 U.S.C. § 112(b) The following is a quotation of 35 U.S.C. § 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 9-13 are rejected under 35 U.S.C. § 112(b) or pre-AIA 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention. As to claim 9, it is unclear how “a first metal interconnection on the IMD layer to electrically connect the FeFET and a source/drain region adjacent to the MOS transistor; and a ferroelectric random access memory (FeRAM) on and directly contacting the first metal interconnection, wherein the FeRAM comprises a second FE layer, a thickness of the second FE layer is greater than twice the thickness of the first FE layer, and a width of the FeRAM is less than a width of the first metal interconnection” (emphasis added). In FIG. 3, a first metal interconnection is necessarily 72 because FeRAM 74 is required to directly contact it. However, a width of the FeRAM at its bottom surface is the same width as that of the first metal interconnection at its top surface, i.e. at the point of contact between the two structures. In FIG. 6, a first metal interconnection is necessarily 138 because FeRAM 160 is required to directly contact it. However, a width of the FeRAM at its bottom surface is the same width as that of the first metal interconnection at its top surface, i.e. at the point of contact between the two structures. Additionally, the first metal interconnection does not electrically connect the FeFET 132 and a source/drain region 114 adjacent to the MOS transistor 108. Indication of Allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: claims 14-17 are indicated as being allowable because prior art fails to teach “wherein the FeRAM and the FeFET are on a same level, a bottom surface of the gate structure is even with a bottom surface of the FeRAM, and top surfaces of the first semiconductor layer and the second semiconductor layer are coplanar” as recited in claim 14. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBERR CHI whose telephone number is (571)270-3955. The examiner can normally be reached 10am to 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUBERR L CHI/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jun 11, 2024
Application Filed
Jul 24, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707848
DISPLAY APPARATUS HAVINGA STRUCTURE CAPBLE OF IMPROVRING LUMINACE
4y 7m to grant Granted Aug 11, 2026
Patent 12696569
SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS
3y 11m to grant Granted Jul 28, 2026
Patent 12685150
EXTENDED VIA CONNECT FOR PIXEL ARRAY
3y 6m to grant Granted Jul 14, 2026
Patent 12672380
PHOTODIODE WITH ORTHOGONAL LAYER STRUCTURE
2y 11m to grant Granted Jun 30, 2026
Patent 12666659
SEMICONDUCTOR MEMORY STRUCTURE HAVING DRAIN STRESSOR, SOURCE STRESSOR AND BURIED GATE AND METHOD OF MANUFACTURING THE SAME
2y 11m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
87%
With Interview (+2.8%)
2y 9m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 653 resolved cases by this examiner. Grant probability derived from career allowance rate.

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