DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/22/2025 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors.
Claim 12 recites the limitation " the top end of the gate dielectric layer is higher than a top surface of the word line is lower” found idiomatic error.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-9,11-14, 16-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Slesazeck (US 2010011753), and further in view of Yamada (US 20010025973).
Regarding claim 1, Slesazeck teaches a manufacturing method of a memory device in figs. 3D-3F, comprising:
forming a trench in a substrate (301);
forming a gate dielectric layer (311) lining the trench;
forming a word line (392) in the trench and over the gate dielectric layer (311);
etching the gate dielectric layer (311) such that a top end of the gate dielectric layer (refer to an upper surface of 311) is lower than a top surface of the substrate (refer to an upper surface of 301) (see fig. 3D);
forming a landing pad (324; see par. 55) over the top end of the gate dielectric layer (refer to the upper surface of 311);
Slesazeck does not mention “forming a dielectric layer covering the word line, the landing pad, and the substrate;
forming a contact in the dielectric layer and in contact with the substrate and the landing pad.”
Yamada teaches the same field of an endeavor wherein forming a dielectric layer (20) covering the word line (refer to WL), and the substrate (1);
forming a contact (BL) in the dielectric layer (20) and in contact with the substrate (1) (see fig. 46).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the a dielectric layer and contact plug of Yamada in the teaching of Slesazeck because the interlayered dielectric layers are commonly placed between conductive layers in integrated circuits to electrical isolate them, prevent shorts and control signal performance and the contact provides electrically connection between the capacitor elements and bitlines (see par. 166).
Adding the dielectric layer (20) and the contact plug (BL) of Yamada into the Slesazeck’ s memory structure such as: forming a dielectric layer covering the word line, the landing pad, and the substrate; forming a contact in the dielectric layer and in contact with the substrate and the landing pad.
Regarding claim 6, Slesazeck and Yamada teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Yamada teaches after etching the gate dielectric layer (8), the top end of the gate dielectric layer (8) is higher than the top surface of the word line (9) and lower than the top surface of the substrate (1) (see fig. 46).
Regarding claim 7, Slesazeck and Yamada teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Yamada teaches forming the contact (BL) comprises: forming an opening in the dielectric layer exposing the substrate (1) and the landing pad (4); and forming the contact in the opening (see fig. 46).
Regarding claim 9, Slesazeck and Yamada teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Yamada teaches a bottom of the landing pad (4) is higher than a top surface of the word line (9) (see fig. 46).
Regarding claim 11, Slesazeck teaches a memory device in figs. 3D-3F, comprising:
a substrate (301);
a word line (392) in the substrate (301);
a gate dielectric layer (311) lining the word line (392);
a landing pad (324; see par. 55) in contact with a top end of the gate dielectric layer (311) and a sidewall of the substrate (301) (see fig. 3F).
Slesazeck does not mention “a dielectric layer covering the word line, the landing pad, and the substrate;
a contact in the dielectric layer and in contact with the substrate and the landing pad.”
Yamada teaches the same field of an endeavor wherein a dielectric layer (20) over the substrate (1 or 3P), the word line (9) and the landing pad (4); and
a contact (BL) in the dielectric layer (20) and in contact with the substrate (1 or 3P).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the a dielectric layer and contact plug of Yamada in the teaching of Slesazeck because the interlayered dielectric layers are commonly placed between conductive layers in integrated circuits to electrical isolate them, prevent shorts and control signal performance and the contact provides electrically connection between the capacitor elements and bitlines (see par. 166).
Adding the dielectric layer (20) and the contact plug (BL) of Yamada into the Slesazeck’ s memory structure such as: a dielectric layer covering the word line, the landing pad, and the substrate; and a contact in the dielectric layer and in contact with the substrate and the landing pad.
Regarding claim 12, Slesazeck and Yamada teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Yamada teaches the top end of the gate dielectric (8) is higher than a top surface of the word line is lower (see fig. 46).
Regarding claim 13, Slesazeck and Yamada teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fig. 46 of Yamada teaches a cap layer (42a) over the word line and covered by the dielectric layer (20), wherein a top surface of the cap layer (42a) is lower than the top surface of the landing pad (refer to Slesazeck’s 354b in fig. 3F).
Regarding claim 14, Slesazeck and Yamada teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fig. 46 of Yamada teaches the top surface of the cap layer (42a) is substantially level with a bottom of the landing pad (refer to Slesazeck’s 354b as shown in fig. 3F).
Regarding claim 16, Slesazeck and Yamada teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 44 of Yamada teaches the landing pad (refer to Slesazeck’s 354b as shown in fig. 3F) is in contact with a sidewall of the dielectric layer (20).
Regarding claim 17, Slesazeck and Yamada teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 45 or 46 of Yamada teaches a bottom of the landing pad (refer to Slesazeck’s 354b as shown in fig. 3F) is higher than a top surface of the word line (9).
Regarding claim 18, Slesazeck and Yamada teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 45 of Yamada teaches the contact (BL) vertically overlaps with the gate dielectric layer (8).
Regarding claim 20, Slesazeck and Yamada teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 45 of Yamada teaches the dielectric layer (20) is in contact with the landing pad (refer to Slesazeck’s 354b as shown in fig. 3F) and the contact (BL).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Slesazeck in view of Yamada as applied to claim 1 above, and further in view of JP reference (JP 3953715 B2).
Regarding claim 10, Slesazeck and Yamada teach all the limitations of the claimed all the limitations of the claimed invention for the same reasons as set forth above except for the landing pad is made of amorphous silicon.
JP reference teaches the same field of an endeavor wherein the landing pad is made of amorphous silicon (see par. 58).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the landing pad is made of amorphous silicon as taught by JP reference in the combined teaching of Yamada and Slesazeck because the amorphous silicon film is a versatile material which is not only used as landing pad but also used as the storage electrode of capacitor as well (see par. 58 and 74). It leads to reduce the cost of manufacturing the device.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Slesazeck in view of Yamada as applied to claim 11 above.
Regarding claim 15, Slesazeck and Yamada teach all the limitations of the claimed invention for the same reasons as set forth above except for a top surface of the landing pad is level with a top surface of the substrate.
Since the landing pad is placed on the upper surface of the substrate and the thickness of the landing pad is in nm unit (see par. 117).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to consider a top surface of the landing pad is level with a top surface of the substrate in Yamada’s teaching so that it reduces the overall thickness of the memory device.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Slesazeck in view of Yamada as applied to claim 11 above, and further in view of JP reference (JP 3953715 B2).
Regarding claim 19, Yamada teaches all the limitations of the claimed all the limitations of the claimed invention for the same reasons as set forth above except for the landing pad is made of amorphous silicon.
JP reference teaches the same field of an endeavor wherein the landing pad is made of amorphous silicon (see par. 58).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the landing pad is made of amorphous silicon as taught by JP reference in the teaching of Yamada because the amorphous silicon film is a versatile material which is not only used as landing pad but also used as the storage electrode of capacitor as well (see par. 58 and 74). It leads to reduce the cost of manufacturing the device.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “forming the landing pad comprises: forming a cap layer over the word line; forming a conductive layer lining the substrate, the gate dielectric layer and the cap layer; and etching the conductive layer until the top surface of the substrate is exposed.” Claims 3-5 include all the limitations of claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
Prosecution Insights