DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claims 7 and 17) It is unclear if “TEOS-based silicon oxide layer” is meant to require that a silicon oxide layer is formed from TEOS, or if the intermediate dielectric layer is formed of both TEOS and silicon oxide.
During examination, the quoted limitation was understood to mean that the intermediate dielectric layer is formed from a silicon oxide layer deposited using TEOS.
Rejection 1/3
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8-9, 11, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. (US 2018/0158728) and Trinh et al. (US 2017/0141300).
(Re Claim 1) Chu teaches a resistive random access memory device, comprising: a first inter-layer dielectric (ILD) layer (112; Fig. 15); a first interconnect structure (114; Fig. 15) disposed in the first ILD layer; a capping layer (120; Fig. 15) disposed on the first interconnect structure and the first ILD layer; an intermediate dielectric layer (130; Fig. 15) disposed on the capping layer; a conductive via (140+155; Fig. 15) disposed in the capping layer and the intermediate dielectric layer, wherein the conductive via comprises a polishing stop layer (142+144; Fig. 15), a barrier layer (146; Fig. 15) on the polishing stop layer, and a tungsten layer (155; Fig. 15) on the barrier layer; and a resistive switching structure (167+175+185; Fig. 15) disposed on the conductive via.
Chu has not been explicitly shown to teach a resistive random access memory device comprising a substrate, wherein the first inter-layer dielectric (ILD) layer is disposed on the substrate.
Trinh teaches forming a substrate (602; Fig. 15), and forming a first interconnect structure (604; Fig. 15) disposed on the substrate.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form a substrate underneath the ILD layer of Chu, as taught by Trinh, as the substrate provides features such as transistors that allow for communication with and control of the resistive switching structure of Chu, and it would also provide physical support to the structure of Chu. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
(Re Claim 8) Modified Chu teaches the resistive random access memory device according to claim 1, wherein the polishing stop layer comprises tantalum nitride (142 contains tantalum nitride; ¶25).
(Re Claim 9) Modified Chu teaches the resistive random access memory device according to claim 1, wherein the barrier layer comprises titanium nitride (¶26).
(Re Claim 11) Chu teaches a method for forming a resistive random access memory device, comprising: forming a first inter-layer dielectric (ILD) (112; Fig. 15); forming a first interconnect structure (114; Fig. 15) in the first ILD layer; forming a capping layer (120; Fig. 15) on the first interconnect structure and the first ILD layer; forming an intermediate dielectric layer (130; Fig. 15) on the capping layer; forming a conductive via (140+155; Fig. 15) in the capping layer and the intermediate dielectric layer, wherein the conductive via comprises a polishing stop layer (142+144; Fig. 15), a barrier layer (146; Fig. 15) on the polishing stop layer, and a tungsten layer (155; Fig. 15)on the barrier layer; and forming a resistive switching structure (167+175+185; Fig. 15) on the conductive via.
Chu as not been explicitly shown to teach a method for forming a resistive random access memory device comprising providing a substrate, wherein the first inter-layer dielectric (ILD) layer is on the substrate.
Trinh teaches forming a substrate (602; Fig. 15), and forming a first interconnect structure (604; Fig. 15) on the substrate.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form a substrate underneath the ILD layer of Chu, as taught by Trinh, as the substrate provides features such as transistors that allow for communication with and control of the resistive switching structure of Chu, and it would also provide physical support to the structure of Chu. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
(Re Claim 18) Modified Chu teaches the method according to claim 11, wherein the polishing stop layer comprises tantalum nitride (142 contains tantalum nitride; ¶25).
(Re Claim 19) Modified Chu teaches the method according to claim 11, wherein the barrier layer comprises titanium nitride (¶26).
Claims 6 and 16 rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. (US 2018/0158728) and Trinh et al. (US 2017/0141300) as applied to claim 1 above, and further in view of Wang et al. (US 2022/0102429).
(Re Claim 6) Modified Chu teaches the resistive random access memory device according to claim 1, but has not been explicitly shown to teach wherein the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer.
Wang teaches forming a capping layer (18; Fig. 9) from nitrogen-doped silicon carbide (¶25).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize nitrogen-doped silicon carbide for forming the capping layer of modified Chu, as taught by Wang, thus causing the capping layer to comprise a nitrogen-doped silicon carbide (NDC) layer, to take advantage of nitrogen-doped silicon carbide’s advantageous diffusion resistance and stability.
(Re Claim 16) Modified Chu teaches the method according to claim 11, but has not been explicitly shown to teach wherein the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer.
Wang teaches forming a capping layer (18; Fig. 9) from nitrogen-doped silicon carbide (¶25).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize nitrogen-doped silicon carbide for forming the capping layer of modified Chu, as taught by Wang, thus causing the capping layer to comprise a nitrogen-doped silicon carbide (NDC) layer, to take advantage of nitrogen-doped silicon carbide’s advantageous diffusion resistance and stability.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Trinh et al. (US 10,176,866) and Chu et al. (US 2018/0158728) as respectively applied to claims 1 and 11 above, and further in view of Chuang et al. (US 2017/0170386), Jonkers et al. (US 5,081,065), and Talwar et al. (US 6,388,297).
(Re Claim 7) Modified Chu teaches the resistive random access memory device according to claim 1, but has not been shown to teach the intermediate dielectric layer comprises a TEOS-based silicon oxide layer.
Chuang teaches that either an SRO or TEOS may be used to form an intermediate dielectric layer (142) utilized as a stop layer for CMP (¶19).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize TEOS to form Chu’s intermediate dielectric layer 130 of modified Chu, as taught by Chuang, as these are art recognized alternative materials for forming layers meant to protect underlying layers against a planarization operation. TEOS may also be used in low-temperature operations. Furthermore, the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Jonkers teaches that a TEOS layer is silicon oxide (col. 4 ln. 35-38).
A PHOSITA would understand that where a TEOS layer is to be formed, this results in a silicon oxide layer, as this is conventional in the art (Jonkers: “dielectric (TEOS) layer 13 of silicon oxide in usual manner” (col. 4 ln. 35-38)).
Talwar teaches that depositing TEOS forms TEOS-based silicon oxide layers (col. 4 ln. 50-55).
A PHOSITA would then also find it obvious that forming the intermediate dielectric layer using TEOS as taught by Chuang will cause the intermediate dielectric layer to comprise a TEOS-based silicon oxide layer as this is a known consequence of utilizing TEOS to form dielectric layers.
(Re Claim 17) Modified Chu teaches the method according to claim 11, but has not been shown to teach the intermediate dielectric layer comprises a TEOS-based silicon oxide layer.
Chuang teaches that either an SRO or TEOS may be used to form an intermediate dielectric layer (142) utilized as a stop layer for CMP (¶19).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize TEOS to form Chu’s intermediate dielectric layer 130 of modified Chu, as taught by Chuang, as these are art recognized alternative materials for forming layers meant to protect underlying layers against a planarization operation. TEOS may also be used in low-temperature operations. Furthermore, the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Jonkers teaches that a TEOS layer is silicon oxide (col. 4 ln. 35-38).
A PHOSITA would understand that where a TEOS layer is to be formed, this results in a silicon oxide layer, as this is conventional in the art (Jonkers: “dielectric (TEOS) layer 13 of silicon oxide in usual manner” (col. 4 ln. 35-38)).
Rejection 2/3
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-14, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Trinh et al. (US 10,176,866), Mikawa et al. (US 2014/0312293), and Chu et al. (US 2018/0158728).
(Re Claim 1) Trinh teaches a resistive random access memory device, comprising: a substrate (102; Fig. 10); a first inter-layer dielectric (ILD) layer (104; Fig. 16) disposed on the substrate; a first interconnect structure (106; Fig. 16) disposed in the first ILD layer; an intermediate dielectric layer (114; Fig. 16); a conductive via (116+118; Fig. 16) disposed in the intermediate dielectric layer, wherein the conductive via comprises a polishing stop layer (116; Fig. 16); and a resistive switching structure (110+120+122+130a+130b+128a+128b+124; Fig. 13-14 and 16) disposed on the conductive via.
Trinh has not been explicitly shown to teach a resistive random access memory device comprising a capping layer disposed on the first interconnect structure and the first ILD layer; the intermediate dielectric layer disposed on the capping layer; a conductive via disposed in the capping layer and the intermediate dielectric layer, wherein the conductive via comprises a barrier layer on the polishing stop layer; and a tungsten layer on the barrier layer.
Mikawa teaches forming a lower electrode (104; Fig. 1) of a resistive switching structure (104+105+106; Fig. 1, ¶55) made from tungsten (¶140).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the lower electrode 118 of Trinh using tungsten as taught by Mikawa, as tungsten is an art recognized alternative to e.g., titanium (Trinh: col. 3 ln. 24-27), and tungsten effectively fills openings for conductive vias (Chu: ¶10). Chu teaches forming a resistive random access memory device comprising a conductive via (140; Fig. 4) comprising a polishing stop layer (142) and a barrier layer (144+146).
A PHOSITA would find it obvious to use form the barrier layer of Chu on the polishing stop layer of modified Trinh to provide for increased adherence of the titanium to the layers within the conductive via (Chu: ¶18).
This results in modified Trinh teaching the conductive via comprises a barrier layer (Chu: 144+146) on the polishing stop layer (Trinh: 116), and a tungsten layer (Trinh’s 118 is formed of tungsten in view of Mikawa) on the barrier layer.
Chu teaches forming a lower electrode (167; Fig. 13) on top of planarized tungsten (155; Fig. 12).
A PHOSITA would find it obvious to form an additional layer 167 on top of modified Trinh’s conductive via element 118 after planarization (Trinh: “A planarization process (e.g., a chemical mechanical planarization process may subsequently be performed after deposition of the second lower electrode film 706 [which becomes 118 as seen in Fig. 16]”), to provide layers suitable for another planarization sequence (Chu: ¶28) before depositing additional layers for the resistive switching structure, allowing for surface flatness that improves device performance (Chu: ¶28).
Doing so results in the resistive switching structure being the combination of Chu’s 167 as seen in Fig. 13 and Trinh’s 110+120+122+130a+130b+128a+128b+124 as seen in Fig. 16, where Chu’s 167 is deposited on Trinh’s 118.
Chu teaches forming a capping layer (120; Fig. 3) and an intermediate dielectric layer (130; Fig. 3), both over an inter-layer dielectric layer (112; Fig. 3).
A PHOSITA would find it obvious to form the dielectric stack 120+130 of Chu instead of the lone intermediate dielectric layer 114 of Trinh on top of the first inter-layer dielectric (ILD) layer, to ensure that polishing occurring at higher levels than Trinh’s layer 114 (Trinh: e.g., see col. 7 ln. 3-5, col. 7 ln. 16-20) does not remove material located in the first inter-layer dielectric layer of modified Trinh (Chu: “As such, if the second dielectric layer 130 did not stop the CMP, the CMP can be stopped by the underlying first dielectric layer 120, and hence damage to the raised metal interconnection lines in other region of the substrate 110 can be mitigated.” (¶24)).
This results in modified Trinh teaching a capping layer (Chu: 120; Fig. 3) disposed on the first interconnect structure and the first ILD layer; an intermediate dielectric layer (Chu: 130; Fig. 3) disposed on the capping layer; and the conductive via disposed in the capping layer and the intermediate dielectric layer (Chu’s 120+130 is located where Trinh’s 114 is).
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(Re Claim 2) Modified Trinh teaches the resistive random access memory device according to claim 1, wherein the conductive via comprises an upper portion (portion above the left and right topmost surfaces of 114; Fig. 16) protruding from a top surface (topmost surface of Chu’s 130) of the intermediate dielectric layer (as a consequence of etching the exposed portions of Chu’s 130 incorporated into modified Trinh, that layer will have a non-zero amount of thickness etched through, causing the conductive via to protrude from the top surface; Trinh: Fig. 14, col. 9 ln. 25-35).
(Re Claim 3) Modified Trinh teaches the resistive random access memory device according to claim 2 further comprising: a sidewall spacer (1502+1504; Fig. 15) disposed around the upper portion of the conductive via and the resistive switching structure (Fig. 16 markup).
(Re Claim 4) Modified Trinh teaches the resistive random access memory device according to claim 3, wherein the sidewall spacer covers a sidewall (left sidewall; Fig. 16) of the resistive switching structure, a sidewall (left sidewall; Fig. 16 markup) of the upper portion of the conductive via, and the top surface (topmost surface is underneath the resistive switching structure; Fig. 16 markup) of the intermediate dielectric layer, and wherein the sidewall spacer is in direct contact with the polishing stop layer (as a consequence of etching; Fig. 16).
(Re Claim 8) Modified Trinh teaches the resistive random access memory device according to claim 1, wherein the polishing stop layer comprises tantalum nitride (col. 2 ln. 21-23).
(Re Claim 9) Modified Trinh teaches the resistive random access memory device according to claim 1, wherein the barrier layer comprises titanium nitride (Chu: ¶17).
(Re Claim 10) Modified Trinh teaches the resistive random access memory device according to claim 3 further comprising: a second inter-layer dielectric (ILD) layer covering the sidewall spacer (1506; Fig. 15); and a second interconnect structure (126; Fig. 16) disposed in the second ILD layer.
(Re Claim 11) Trinh teaches a method for forming a resistive random access memory device, comprising: providing a substrate (102; Fig. 10); forming a first inter-layer dielectric (ILD) layer (104; Fig. 16) on the substrate; forming a first interconnect structure (106; Fig. 16) in the first ILD layer; forming an intermediate dielectric layer (114; Fig. 16); forming a conductive via (116+118; Fig. 16) in the intermediate dielectric layer, wherein the conductive via comprises a polishing stop layer (116; Fig. 16); and
forming a resistive switching structure (110+120+122+130a+130b+128a+128b+124; Fig. 13-14 and 16) on the conductive via.
Trinh has not been explicitly shown to teach a method for forming a resistive random access memory device comprising forming a capping layer on the first interconnect structure and the first ILD layer; forming an intermediate dielectric layer on the capping layer; forming the conductive via in the capping layer and the intermediate dielectric layer, wherein the conductive via comprising a barrier layer on the polishing stop layer and a tungsten layer on the barrier layer.
Mikawa teaches forming a lower electrode (104; Fig. 1) of a resistive switching structure (104+105+106; Fig. 1, ¶55) made from tungsten (¶140).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the lower electrode 118 of Trinh using tungsten as taught by Mikawa, as tungsten is an art recognized alternative to e.g., titanium (Trinh: col. 3 ln. 24-27), and tungsten effectively fills openings for conductive vias (Chu: ¶10). Chu teaches forming a resistive random access memory device comprising a conductive via (140; Fig. 4) comprising a polishing stop layer (142) and a barrier layer (144+146).
A PHOSITA would find it obvious to use form the barrier layer of Chu on the polishing stop layer of modified Trinh to provide for increased adherence of the titanium to the layers within the conductive via (Chu: ¶18).
This results in modified Trinh teaching the conductive via comprises a barrier layer (Chu: 144+146) on the polishing stop layer (Trinh: 116), and a tungsten layer (Trinh’s 118 is formed of tungsten in view of Mikawa) on the barrier layer.
Chu teaches forming a lower electrode (167; Fig. 13) on top of planarized tungsten (155; Fig. 12).
A PHOSITA would find it obvious to form an additional layer 167 on top of modified Trinh’s conductive via element 118 after planarization (Trinh: “A planarization process (e.g., a chemical mechanical planarization process may subsequently be performed after deposition of the second lower electrode film 706 [which becomes 118 as seen in Fig. 16]”), to provide layers suitable for another planarization sequence (Chu: ¶28) before depositing additional layers for the resistive switching structure, allowing for surface flatness that improves device performance (Chu: ¶28).
Doing so results in the resistive switching structure being the combination of Chu’s 167 as seen in Fig. 13 and Trinh’s 110+120+122+130a+130b+128a+128b+124 as seen in Fig. 16, where Chu’s 167 is deposited on Trinh’s 118.
Chu teaches forming a capping layer (120; Fig. 3) and an intermediate dielectric layer (130; Fig. 3), both over an inter-layer dielectric layer (112; Fig. 3).
A PHOSITA would find it obvious to form the dielectric stack 120+130 of Chu instead of the lone intermediate dielectric layer 114 of Trinh on top of the first inter-layer dielectric (ILD) layer, to ensure that polishing occurring at higher levels than Trinh’s layer 114 (Trinh: e.g., see col. 7 ln. 3-5, col. 7 ln. 16-20) does not remove material located in the first inter-layer dielectric layer of modified Trinh (Chu: “As such, if the second dielectric layer 130 did not stop the CMP, the CMP can be stopped by the underlying first dielectric layer 120, and hence damage to the raised metal interconnection lines in other region of the substrate 110 can be mitigated.” (¶24)).
This results in modified Trinh teaching a capping layer (Chu: 120; Fig. 3) disposed on the first interconnect structure and the first ILD layer; an intermediate dielectric layer (Chu: 130; Fig. 3) disposed on the capping layer; and the conductive via disposed in the capping layer and the intermediate dielectric layer (Chu’s 120+130 is located where Trinh’s 114 is).
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(Re Claim 12) Modified Trinh teaches the method according to claim 11, wherein the conductive via comprises an upper portion (portion above the left and right topmost surfaces of 114; Fig. 16) protruding from a top surface (topmost surface of Chu’s 130) of the intermediate dielectric layer (as a consequence of etching the exposed portions of Chu’s 130 incorporated into modified Trinh, that layer will have a non-zero amount of thickness etched through, causing the conductive via to protrude from the top surface; Trinh: Fig. 14, col. 9 ln. 25-35).
(Re Claim 13) Modified Trinh teaches the method according to claim 12 further comprising: forming a sidewall spacer (1502+1504; Fig. 15) around the upper portion of the conductive via and the resistive switching structure (Fig. 16 markup).
(Re Claim 14) Modified Trinh teaches the method according to claim 13, wherein the sidewall spacer covers a sidewall of the resistive switching structure (left sidewall; Fig. 16), a sidewall of the upper portion of the conductive via (left sidewall; Fig. 16 markup), and the top surface of the intermediate dielectric layer (from the left side; Fig. 16 markup), and wherein the sidewall spacer is in direct contact with the polishing stop layer (as a consequence of etching; Fig. 16).
(Re Claim 18) Modified Trinh teaches the method according to claim 11, wherein the polishing stop layer comprises tantalum nitride (col. 2 ln. 21-23).
(Re Claim 19) Modified Trinh teaches the method according to claim 11, wherein the barrier layer comprises titanium nitride (Chu: ¶17).
(Re Claim 20) Modified Trinh teaches the method according to claim 13 further comprising: forming a second inter-layer dielectric (ILD) layer (1506; Fig. 15) on the sidewall spacer; and forming a second interconnect structure in the second ILD layer (126; Fig. 16).
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Trinh et al. (US 10,176,866), Mikawa et al. (US 2014/0312293), and Chu et al. (US 2018/0158728) as respectively applied to claims 3 and 13 above, and further in view of Chen et al. (US 2023/0284540).
(Re Claim 5) Modified Trinh teaches the resistive random access memory device according to claim 3, but has not been explicitly shown to teach the sidewall spacer layer comprises a silicon nitride layer and a silicon oxide layer.
The sidewall spacer layer of Trinh is divided into two sections (1502 and 1504; Fig. 15).
Chen teaches forming a sidewall spacer layer (129+131; Fig. 19) using silicon oxide (¶94).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize silicon oxide to form the outer section of Trinh’s sidewall spacer layer, as taught by Chen, to reduce stress between the inner section and other dielectrics deposited layer in the manufacturing sequence (Chen: ¶94). This causes Trinh’s 1504 to be a silicon oxide layer.
Chu teaches forming a sidewall spacer layer (200; Fig. 15) using silicon nitride.
A PHOSITA would find it obvious to form the inner section of Trinh’s sidewall spacer layer using silicon nitride, in the manner taught by Chu, to provide for an etch stop layer (Chu: ¶39), allowing for greater contact depth control. This causes Trinh’s 1502 to be a silicon nitride layer.
(Re Claim 15) Modified Trinh teaches the method according to claim 13, but has not been shown to teach the sidewall spacer layer comprises a silicon nitride layer and a silicon oxide layer.
The sidewall spacer layer of Trinh is divided into two sections (1502 and 1504; Fig. 15).
Chen teaches forming a sidewall spacer layer (129+131; Fig. 19) using silicon oxide (¶94).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize silicon oxide to form the outer section of Trinh’s sidewall spacer layer, as taught by Chen, to reduce stress between the inner section and other dielectrics deposited layer in the manufacturing sequence (Chen: ¶94). This causes Trinh’s 1504 to be a silicon oxide layer.
Chu teaches forming a sidewall spacer layer (200; Fig. 15) using silicon nitride.
A PHOSITA would find it obvious to form the inner section of Trinh’s sidewall spacer layer using silicon nitride, in the manner taught by Chu, to provide for an etch stop layer (Chu: ¶39), allowing for greater contact depth control. This causes Trinh’s 1502 to be a silicon nitride layer.
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Trinh et al. (US 10,176,866), Mikawa et al. (US 2014/0312293), and Chu et al. (US 2018/0158728) as respectively applied to claims 1 and 11 above, and further in view of Wang et al. (US 2022/0102429).
(Re Claim 6) Modified Trinh teaches the resistive random access memory device according to claim 1, but has not been shown to teach the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer.
Wang teaches forming a capping layer (18; Fig. 9) from nitrogen-doped silicon carbide (¶25).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize nitrogen-doped silicon carbide for forming the capping layer of modified Trinh, as taught by Wang, thus causing the capping layer to comprise a nitrogen-doped silicon carbide (NDC) layer, to take advantage of nitrogen-doped silicon carbide’s advantageous diffusion resistance and stability.
(Re Claim 16) Modified Trinh teaches the method according to claim 11, but has not been shown to teach the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer.
Wang teaches forming a capping layer (18; Fig. 9) from nitrogen-doped silicon carbide (¶25).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize nitrogen-doped silicon carbide for forming the capping layer of modified Trinh, as taught by Wang, thus causing the capping layer to comprise a nitrogen-doped silicon carbide (NDC) layer, to take advantage of nitrogen-doped silicon carbide’s advantageous diffusion resistance and stability.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Trinh et al. (US 10,176,866), Mikawa et al. (US 2014/0312293), and Chu et al. (US 2018/0158728) as respectively applied to claims 1 and 11 above, and further in view of Chuang et al. (US 2017/0170386), Jonkers et al. (US 5,081,065), and Talwar et al. (US 6,388,297).
(Re Claim 7) Modified Trinh teaches the resistive random access memory device according to claim 1, but has not been shown to teach the intermediate dielectric layer comprises a TEOS-based silicon oxide layer.
Chuang teaches that either an SRO or TEOS may be used to form an intermediate dielectric layer (142) utilized as a stop layer for CMP (¶19).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize TEOS to form Chu’s intermediate dielectric layer 130 of modified Trinh, as taught by Chuang, as these are art recognized alternative materials for forming layers meant to protect underlying layers against a planarization operation. TEOS may also be used in low-temperature operations. Furthermore, the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Jonkers teaches that a TEOS layer is silicon oxide (col. 4 ln. 35-38).
A PHOSITA would understand that where a TEOS layer is to be formed, this results in a silicon oxide layer, as this is conventional in the art (Jonkers: “dielectric (TEOS) layer 13 of silicon oxide in usual manner” (col. 4 ln. 35-38)).
Talwar teaches that depositing TEOS forms TEOS-based silicon oxide layers (col. 4 ln. 50-55).
A PHOSITA would then also find it obvious that forming the intermediate dielectric layer using TEOS as taught by Chuang will cause the intermediate dielectric layer to comprise a TEOS-based silicon oxide layer as this is a known consequence of utilizing TEOS to form dielectric layers.
(Re Claim 17) Modified Trinh teaches the method according to claim 11, but has not been shown to teach the intermediate dielectric layer comprises a TEOS-based silicon oxide layer.
Chuang teaches that either an SRO or TEOS may be used to form an intermediate dielectric layer (142) utilized as a stop layer for CMP (¶19).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize TEOS to form Chu’s intermediate dielectric layer 130 of modified Trinh, as taught by Chuang, as these are art recognized alternative materials for forming layers meant to protect underlying layers against a planarization operation. TEOS may also be used in low-temperature operations. Furthermore, the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Jonkers teaches that a TEOS layer is silicon oxide (col. 4 ln. 35-38).
A PHOSITA would understand that where a TEOS layer is to be formed, this results in a silicon oxide layer, as this is conventional in the art (Jonkers: “dielectric (TEOS) layer 13 of silicon oxide in usual manner” (col. 4 ln. 35-38)).
Talwar teaches that depositing TEOS forms TEOS-based silicon oxide layers (col. 4 ln. 50-55).
A PHOSITA would then also find it obvious that forming the intermediate dielectric layer using TEOS as taught by Chuang will cause the intermediate dielectric layer to comprise a TEOS-based silicon oxide layer as this is a known consequence of utilizing TEOS to form dielectric layers.
Rejection 3/3
Claims 1-2, 8-9, 11-12, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hayakawa et al. (US 2015/0263279), Trinh et al. (US 10,176,866), and Chu et al. (US 2018/0158728).
(Re Claim 1) Hayawaka teaches a resistive random access memory device, comprising: a first inter-layer dielectric (ILD) layer (106; Fig. 15); a first interconnect structure (103+104; Fig. 15) disposed in the first ILD layer; a capping layer (105; Fig. 15) disposed on the first interconnect structure and the first ILD layer; an intermediate dielectric layer (106; Fig. 15) disposed on the capping layer; a conductive via (108+109; Fig. 15) disposed in the capping layer and the intermediate dielectric layer, wherein the conductive via comprises a polishing stop layer (108; ¶120), and a tungsten layer (109 may be tungsten as described in ¶83) on the barrier layer; and a resistive switching structure (113; Fig. 15) disposed on the conductive via.
Hayawaka has not been shown to teach a device comprising a substrate; the first inter-layer dielectric (ILD) layer disposed on the substrate; and the conductive via comprises a barrier layer on the polishing stop layer.
Trinh teaches providing a substrate (102; Fig. 10) and forming a first inter-layer dielectric (ILD) layer (104; Fig. 16) on the substrate.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to position a substrate beneath the ILD layer of Hayawaka, as taught by Trinh, to provide a base on which layers are sequentially deposited and provide support to those layers as they are added.
Chu teaches forming a conductive via (140+155; Fig. 6) using a barrier layer (144+146; Fig. 6) on a polishing stop layer (142; Fig. 6).
A PHOSITA would find it obvious to deposit a barrier layer as taught by Chu on the polishing stop layer of Hayawaka before forming the tungsten layer of Hayawaka, to allow for good adhesion between the tungsten layer and the polishing stop layer (Chu: ¶17).
As Hayawaka teaches planarizing the conductive via using the polishing stop layer 108 remains exposed after the polish but otherwise removes material in the conductive via to at least a position level with the top surface of the polishing stop layer 108 (¶120), a PHOSITA would find it obvious to have the polishing stop layer 108 exposed on the upper surface of the intermediate dielectric layer, while polishing away the barrier layer and tungsten layer outside of the conductive via opening (107; Fig. 8), to suppress level differences (¶121).
(Re Claim 2) Modified Hayawaka teaches the resistive random access memory device according to claim 1, wherein the conductive via comprises an upper portion (108 contacting the uppermost surface of the intermediate dielectric layer; Fig. 15) protruding from a top surface (the uppermost surface of the intermediate dielectric layer) of the intermediate dielectric layer.
(Re Claim 8) Modified Hayawaka teaches the resistive random access memory device according to claim 1, wherein the polishing stop layer comprises tantalum nitride (¶82).
(Re Claim 9) Modified Hayawaka teaches the resistive random access memory device according to claim 1, wherein the barrier layer comprises titanium nitride (Chu: ¶17).
(Re Claim 11) Hayawaka teaches a method for forming a resistive random access memory device, comprising: forming a first inter-layer dielectric (ILD) layer (106; Fig. 15) on the substrate; forming a first interconnect structure (103+104; Fig. 15) in the first ILD layer; forming a capping layer (105; Fig. 15) on the first interconnect structure and the first ILD layer; forming an intermediate dielectric layer (106; Fig. 15) on the capping layer; forming a conductive via (108+109; Fig. 15) in the capping layer and the intermediate dielectric layer, wherein the conductive via comprises a polishing stop layer (108; ¶120) and a tungsten layer (109 may be tungsten as described in ¶83); and forming a resistive switching structure (113; Fig. 13)on the conductive via.
Hayawaka has not been shown to teach forming a resistive random access memory device comprising providing a substrate; forming a first inter-layer dielectric (ILD) layer on the substrate, wherein the conductive via comprises a barrier layer on the polishing stop layer and the tungsten layer on the barrier.
Trinh teaches providing a substrate (102; Fig. 10) and forming a first inter-layer dielectric (ILD) layer (104; Fig. 16) on the substrate.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to position a substrate beneath the ILD layer of Hayawaka, as taught by Trinh, to provide a base on which layers are sequentially deposited and provide support to those layers as they are added.
Chu teaches forming a conductive via (140+155; Fig. 6) using a barrier layer (144+146; Fig. 6) on a polishing stop layer (142; Fig. 6).
A PHOSITA would find it obvious to deposit a barrier layer as taught by Chu on the polishing stop layer of Hayawaka before forming the tungsten layer of Hayawaka, to allow for good adhesion between the tungsten layer and the polishing stop layer (Chu: ¶17).
As Hayawaka teaches planarizing the conductive via using the polishing stop layer 108 remains exposed after the polish but otherwise removes material in the conductive via to at least a position level with the top surface of the polishing stop layer 108 (¶120), a PHOSITA would find it obvious to have the polishing stop layer 108 exposed on the upper surface of the intermediate dielectric layer, while polishing away the barrier layer and tungsten layer outside of the conductive via opening (107; Fig. 8), to suppress level differences (¶121).
(Re Claim 12) Modfied Hayawaka teaches the method according to claim 11, wherein the conductive via comprises an upper portion portion (108 contacting the uppermost surface of the intermediate dielectric layer; Fig. 15) protruding from a top surface (the uppermost surface of the intermediate dielectric layer) of the intermediate dielectric layer.
(Re Claim 18) Modified Hayawaka teaches the method according to claim 11, wherein the polishing stop layer comprises tantalum nitride (¶82).
(Re Claim 19) Modified Hayawaka teaches the method according to claim 11, wherein the barrier layer comprises titanium nitride (Chu: ¶17).
Claims 3-5, 10, 13-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hayakawa et al. (US 2015/0263279), Trinh et al. (US 10,176,866), and Chu et al. (US 2018/0158728) as respectively applied to claims 2 and 12 above, and further in view of Chen et al. (US 2023/0284540).
(Re Claim 3) Modified Hayawaka teaches the resistive random access memory device according to claim 2 but has not been shown to teach the device further comprising: a sidewall spacer disposed around the upper portion of the conductive via and the resistive switching structure.
Chen teaches forming a sidewall spacer (129+131; Fig. 19) around an upper portion (portion of 109 above 105) of a conductive via (109; Fig. 19) and a resistive switching structure (111+1113+115+117+123; Fig. 19)
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to deposit a sidewall spacer around the upper portion of the conductive via and the resistive switching structure of modified Hayawaka, as taught by Chen, to provide an etch stop (Chen: ¶93) for improving depth control for forming a top contact to the resistive switching structure, and to reduce stress between the etch stop part 129 of the sidewall spacer and additional dielectrics subsequently deposited on the sidewall spacer (Chen: ¶94).
(Re Claim 4) Modified Hayawaka teaches the resistive random access memory device according to claim 3, wherein the sidewall spacer covers a sidewall of the resistive switching structure (left sidewall; Fig. 15), a sidewall of the upper portion of the conductive via (left sidewall of 108; Fig. 19), and the top surface of the intermediate dielectric layer (Fig. 15), and wherein the sidewall spacer is in direct contact with the polishing stop layer (Fig. 15).
(Re Claim 5) Modified Hayawaka teaches the method according to claim 13, wherein the sidewall spacer layer comprises a silicon oxide layer (Chen: 131 is silicon oxide; ¶94) but has not been shown to teach the sidewall spacer layer comprises a silicon nitride layer
Chu teaches forming a sidewall spacer layer (200; Fig. 15) using silicon nitride.
A PHOSITA would find it obvious to form the inner section 129 of modified Hayawaka’s sidewall spacer layer using silicon nitride, in the manner taught by Chu, to provide for an etch stop layer (Chu: ¶39), allowing for greater contact depth control. This causes modified Hayawaka’s 129 from Chu to be a silicon nitride layer.
(Re Claim 10) Modified Hayawaka teaches the resistive random access memory device according to claim 3 further comprising: a second inter-layer dielectric (ILD) layer (114; Fig. 15) covering the sidewall spacer; and a second interconnect structure (116+117; Fig. 15) disposed in the second ILD layer.
(Re Claim 13) Modified Hayawaka teaches the method according to claim 12 but has not been shown to teach the method further comprising: forming a sidewall spacer around the upper portion of the conductive via and the resistive switching structure.
Chen teaches forming a sidewall spacer (129+131; Fig. 19) around an upper portion (portion of 109 above 105) of a conductive via (109; Fig. 19) and a resistive switching structure (111+1113+115+117+123; Fig. 19)
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to deposit a sidewall spacer around the upper portion of the conductive via and the resistive switching structure of modified Hayawaka, as taught by Chen, to provide an etch stop (Chen: ¶93) for improving depth control for forming a top contact to the resistive switching structure, and to reduce stress between the etch stop part 129 of the sidewall spacer and additional dielectrics subsequently deposited on the sidewall spacer (Chen: ¶94).
(Re Claim 14) Modified Hayawaka teaches the method according to claim 13, wherein the sidewall spacer covers a sidewall (left sidewall; Fig. 15) of the resistive switching structure, a sidewall (left sidewall of 108; Fig. 15) of the upper portion of the conductive via, and the top surface of the intermediate dielectric layer (Fig. 15), and wherein the sidewall spacer is in direct contact with the polishing stop layer (Fig. 15).
(Re Claim 15) Modified Hayawaka teaches the method according to claim 13, wherein the sidewall spacer layer comprises a silicon oxide layer (Chen: 131 is silicon oxide; ¶94) but has not been shown to teach the sidewall spacer layer comprises a silicon nitride layer
Chu teaches forming a sidewall spacer layer (200; Fig. 15) using silicon nitride.
A PHOSITA would find it obvious to form the inner section 129 of modified Hayawaka’s sidewall spacer layer using silicon nitride, in the manner taught by Chu, to provide for an etch stop layer (Chu: ¶39), allowing for greater contact depth control. This causes modified Hayawaka’s 129 from Chu to be a silicon nitride layer.
(Re Claim 20) Modified Hayawaka teaches the method according to claim 13 further comprising: forming a second inter-layer dielectric (ILD) layer (114l; Fig. 15) on the sidewall spacer; and forming a second interconnect structure (116+117; Fig. 15) in the second ILD layer.
Claims 6 and 16 rejected under 35 U.S.C. 103 as being unpatentable over Hayakawa et al. (US 2015/0263279), Trinh et al. (US 10,176,866), and Chu et al. (US 2018/0158728) as respectively applied to claims 1 and 11 above, and further in view of Wang et al. (US 2022/0102429).
(Re Claim 6) Modified Hayawaka teaches the resistive random access memory device according to claim 1, but has not been shown to teach the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer.
Wang teaches forming a capping layer (18; Fig. 9) from nitrogen-doped silicon carbide (¶25).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize nitrogen-doped silicon carbide for forming the capping layer of modified Hayawaka, as taught by Wang, thus causing the capping layer to comprise a nitrogen-doped silicon carbide (NDC) layer, to take advantage of nitrogen-doped silicon carbide’s advantageous diffusion resistance and stability.
(Re Claim 16) Modified Hayawaka teaches the method according to claim 11, but has not been shown to teach the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer.
Wang teaches forming a capping layer (18; Fig. 9) from nitrogen-doped silicon carbide (¶25).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize nitrogen-doped silicon carbide for forming the capping layer of modified Hayawaka, as taught by Wang, thus causing the capping layer to comprise a nitrogen-doped silicon carbide (NDC) layer, to take advantage of nitrogen-doped silicon carbide’s advantageous diffusion resistance and stability.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hayakawa et al. (US 2015/0263279), Trinh et al. (US 10,176,866), and Chu et al. (US 2018/0158728) as respectively applied to claims 1 and 11 above, and further in view of Jonkers et al. (US 5,081,065) and Talwar et al. (US 6,388,297).
(Re Claim 7) Modified Hayawaka teaches the resistive random access memory device according to claim 1, but has not been shown to teach the intermediate dielectric layer comprises a TEOS-based silicon oxide layer.
However, the intermediate dielectric layer of Hayawaka is formed from silicon oxide (¶80).
Jonkers teaches that a dielectric layer of silicon oxide from TEOS is conventional (col. 4 ln. 35-38).
A PHOSITA would understand that where a silicon oxide layer is formed from TEOS, as this is conventional in the art (Jonkers: “dielectric (TEOS) layer 13 of silicon oxide in usual manner” (col. 4 ln. 35-38)).
Talwar teaches that depositing TEOS forms TEOS-based silicon oxide layers (col. 4 ln. 50-55).
A PHOSITA would then also find it obvious that forming the intermediate dielectric layer using TEOS as taught by Chuang will cause the intermediate dielectric layer to comprise a TEOS-based silicon oxide layer as this is a known consequence of utilizing TEOS to form dielectric layers.
(Re Claim 17) Modified Hayawaka teaches the method according to claim 11, but has not been shown to teach the intermediate dielectric layer comprises a TEOS-based silicon oxide layer.
However, the intermediate dielectric layer of Hayawaka is formed from silicon oxide (¶80).
Jonkers teaches that a dielectric layer of silicon oxide from TEOS is conventional (col. 4 ln. 35-38).
A PHOSITA would understand that where a silicon oxide layer is formed from TEOS, as this is conventional in the art (Jonkers: “dielectric (TEOS) layer 13 of silicon oxide in usual manner” (col. 4 ln. 35-38)).
Talwar teaches that depositing TEOS forms TEOS-based silicon oxide layers (col. 4 ln. 50-55).
A PHOSITA would then also find it obvious that forming the intermediate dielectric layer using TEOS as taught by Chuang will cause the intermediate dielectric layer to comprise a TEOS-based silicon oxide layer as this is a known consequence of utilizing TEOS to form dielectric layers.
Conclusion
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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