DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-16 in the reply filed on August 31st 2026 is acknowledged. Therefore claims 17-20 are hereby withdrawn.
Applicant’s amendment to add new claims 21-24 is also acknowledged and they correspond to elected Group I. Therefore 1-16 & 21-24 are examined below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, 11, & 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw (US 20230032523).
Regarding claim 1, Liaw teaches a semiconductor device, comprising:
a first memory cell including a first active region for n-type transistors and a second active region for p-type transistors (Fig 7 shows a first memory cell, 152, has a first active region, 215J and a second active region, 215I. Paragraph 0022 describes that P-wells are configured for n-type transistors and the N-wells are designed for P-type transistors. As Fig 7 shows 215J in the P-type well and 215I in the N-type well, the first active region, 215J, contains n-type transistors, and the second active region, 215I contains p-type transistors), the first active region having a first width (The first active region, 215J, has the first width, W5), the second active region having a second width (The second active region, 215I, has the second width W6), the first width being larger than the second width (Fig 7 shows that the first width, W5, is larger than the second width, W6); and
a second memory cell including a third active region for n-type transistors and a fourth active region for p-type transistors (Fig 3 shows a second memory cell, 102, has a third active region, 215E and a fourth active region, 215D. Paragraph 0022 describes that P-wells are configured for n-type transistors and the N-wells are designed for P-type transistors. As Fig 3 shows 215E in the P-type well and 215D in the N-type well, the first active region, 215E, contains n-type transistors, and the second active region, 215D contains p-type transistors), the third active region having a third width (The third active region 215E has the third width, W2), the fourth active region having a fourth width (The fourth active region, 215D, has the fourth width, W3), the third width being larger than the fourth width (Fig. 3 shows that the third width, W2, is larger than the fourth width, W3),
wherein the first width is larger than the third width (Paragraph 0041 states that the first width, W5, is greater than the third width, W2).
Regarding claim 2, Liaw teaches the first memory cell is in a first cache, the second memory is in a second cache, and the first cache has a higher tier than the second cache (Because Liaw shares the same structure within the claimed structure of claim 1, the first memory cell would be able to function as a first cache and the second memory cell would be able to function as a second cache different from the first cache).
Regarding claim 3, Liaw teaches the first memory cell is in a level-1 cache, and the second memory cell is in a level-2 cache (Because Liaw shares the same structure within the claimed structure of claim 1, the first memory cell would be able to function as a level-1 cache and the second memory cell would be able to function as a level-2 cache. The last sentence of paragraph 1 also shows that these levels are well known in the art).
Regarding claim 4, Liaw teaches the first memory cell is in a level-2 cache, and the second memory cell is in a level-3 cache (Because Liaw shares the same structure within the claimed structure of claim 1, the first memory cell would be able to function as a level-2 cache and the second memory cell would be able to function as a level-3 cache. The last sentence of paragraph 1 also shows that these levels are well known in the art).
Regarding claim 5, Liaw teaches the first memory cell and the second memory cell are in the same cache (Because Liaw shares the same structure within the claimed structure of claim 1, the first memory cell and the second memory cell would be able to function as part of the same cache).
Regarding claim 6, Liaw teaches the first memory cell has a first cell width and a first cell height (Y2 being the first width and X2 being the first height), the second memory cell has a second cell width and a second cell height (Y1 being the second width, and X1 being the second height), and the first cell height is larger than the second cell height (Paragraph 0038 states that a ratio of X2 to X1 is greater than 1.05, meaning that the height of X2, the first height, is greater than that of X1, the second height).
Regarding claim 7, Liaw teaches the first cell width substantially equal the second cell width (Paragraph 0038 states that the first width, Y2, and the second width, Y1, are substantially equal).
Regarding claim 8, Liaw teaches wherein the second width substantially equals the fourth width (Paragraph 0041 states that the second width and the fourth width are about the same width, W3 and W6).
Regarding claim 11, Liaw teaches a memory device, comprising:
a first memory cell, the first memory cell including a first pull-down transistor and a first pull-up transistor (Fig 7 shows a first memory cell, 152, has a first active region, 215J and a second active region, 215I. Paragraph 0016 states that 215J is a pull-down transistor and that 215I is a pull-up transistor), the first pull-down transistor having a first channel region of a first width (The first active region, 215J, has the first width, W5), the first pull-up transistor having a second channel region of a second width (The second active region, 215I, has the second width W6), the first width being larger than the second width (Fig 7 shows that the first width, W5, is larger than the second width, W6); and
a second memory cell, the second memory cell including a second pull-down transistor and a second pull-up transistor (Fig 3 shows a second memory cell, 102, has a third active region, 215E and a fourth active region, 215D. Paragraph 0016 states that 215E is a pull-down transistor and that 215D is a pull-up transistor), the second pull-down transistor having a third channel region of a third width (The third active region 215E has the third width, W2), the second pull-up transistor having a fourth channel region of a fourth width The fourth active region, 215D, has the fourth width, W3), the third width being larger than the fourth width (Fig. 3 shows that the third width, W2, is larger than the fourth width, W3),
wherein the first width is larger than the third width (Paragraph 0041 states that the first width, W5, is greater than the third width, W2).
Regarding claim 15, Liaw teaches a ratio of the second width over the fourth width being about 1:1(Paragraph 0041 states that the second width and the fourth width are about the same width).
Regarding claim 16, Liaw teaches each of the first, second, third, and fourth channel regions comprises a plurality of nanostructures vertically stacked (Figs 3 and 7 show each of the channel regions having a plurality of vertically stacked nanostructures, which are pointed to using 215A-J. Paragraph 0014 also describes the transistors having vertically stacked nanowires/nanosheets).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 20230032523) in view of Liaw (US 20200135740 A1).
Regarding claim 9, Liaw does not teach a third memory cell including a fifth active region for n-type transistors and a sixth active region for p-type transistors, the fifth active region having a fifth width, the sixth active region having a sixth width,
wherein the fifth width substantially equals the sixth width.
Liaw in a second reference teaches a third memory cell (Paragraph 0052 states that the memory device contains a third plurality of SRAM cells, therefore contains a third memory cell) including a fifth active region for n-type transistors and a sixth active region for p-type transistors (Fig 2A shows one of the memory cells, 200. The memory cell contains a pull-down transistor, 212, which correlates to the fifth active region, and a pull-up transistor, 208, which correlates to the sixth active region. Paragraph 0023 states that the pull-down transistor is a n-type type and the pull-up transistor is a p-type), the fifth active region having a fifth width, the sixth active region having a sixth width,
wherein the fifth width substantially equals the sixth width (Paragraph 0027 states that the ratio of the fifth width, W1, over the sixth width, W3 is about 1.0).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Liaw to add another memory cell, as taught in the second Liaw reference, because adding a third memory cell allows for the memory device to hold more data, enabling a higher capacity.
It would have further been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Liaw to have the ratio of the fifth and sixth width to have a ratio of 1:1, as taught in the second Liaw reference, because having the two widths be the same helps maintain uniform signal integrity across the cell, improving the reliability of the memory cell.
Regarding claim 10, Liaw, as modified, teaches the second width and the fourth width being substantially equal to each other (Paragraph 0041 states that the second width, W6, and the fourth width, W3, are about the same width).
Liaw does not explicitly teach that the sixth width is equal to the second and fourth width (As the sixth width, which is also the width of a p-type transistor like the second and fourth width, is within the memory cell that is added with the modification made by the second Liaw reference).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the sixth width be the same as the second and fourth width when the third memory cell is introduced by the second Liaw reference because having each of the p-type transistors be the same width would simplify the manufacturing process, reducing the chance of defects in the manufacturing.
Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 20230032523).
Regarding claim 12, Liaw teaches a ratio of the third width over the first width ranging from about 0.6 to about 0.9 (Paragraph 0041 states that the range for the ratio of the first width over the second width is within the range of 1.2 to 5. If we reverse this so that the ratio is the third width over the first width that range becomes roughly 0.2 to 0.83. If we take about to be within 10%, the upper degree of the range, 0.83, fits within that range. Therefore, the ratio of about 0.6-0.9 fits within the range of the ratio in Liaw).
As cited from MPEP 2144.05, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (The prior art taught carbon monoxide concentrations of "about 1-5%" while the claim was limited to "more than 5%." The court held that "about 1-5%" allowed for concentrations slightly above 5% thus the ranges overlapped.); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997) (Claim reciting thickness of a protective layer as falling within a range of "50 to 100 Angstroms" considered prima facie obvious in view of prior art reference teaching that "for suitable protection, the thickness of the protective layer should be not less than about 10 nm [i.e., 100 Angstroms]." The court stated that "by stating that ‘suitable protection’ is provided if the protective layer is ‘about’ 100 Angstroms thick, [the prior art reference] directly teaches the use of a thickness within [applicant’s] claimed range.").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have Liaw choose the higher end of the range because having the ratio of the width for the two pull-down transistors be closer to 1 because it allows for the two pull-down transistors to have similar resistance and capacitance, allowing for better consistency throughout the memory device.
Regarding claim 13, Liaw teaches the ratio of the first width over the second width ranging from about 2 to about 3 (Paragraph 0041 states that the ratio for W4:W6 [W6 being the second width] is between 1.5-5. The beginning of that same paragraph also states that the widths of W4 and W5 [W5 being the first width] are roughly equal. Therefore, the range for the ratio of width one over width two would be the same, 1.5-5. This range would include the range of the ratio of widths 2-3.)
As cited from MPEP 2144.05, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (The prior art taught carbon monoxide concentrations of "about 1-5%" while the claim was limited to "more than 5%." The court held that "about 1-5%" allowed for concentrations slightly above 5% thus the ranges overlapped.); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997) (Claim reciting thickness of a protective layer as falling within a range of "50 to 100 Angstroms" considered prima facie obvious in view of prior art reference teaching that "for suitable protection, the thickness of the protective layer should be not less than about 10 nm [i.e., 100 Angstroms]." The court stated that "by stating that ‘suitable protection’ is provided if the protective layer is ‘about’ 100 Angstroms thick, [the prior art reference] directly teaches the use of a thickness within [applicant’s] claimed range.").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have Liaw choose the center of that range so that it is between 2-3 because having a larger pull-down transistor can increase the current available which can improve the noise margin of the cell, helping to maintain data integrity. But if the pull-down transistor is too much wider than the pull-up transistor that can result in higher voltage and gate capacitance which could result in lower reading speeds, decreasing the overall performance of the memory cell.
Regarding claim 14, Liaw teaches the ratio of the third width over the fourth width ranging from about 1.5 to about 2 (Paragraph 0019 states that the ratio of W2, the third width, over W1 is between 1.05 to 1.5. Paragraph 0020 states that W3, the fourth width, is less than or equal to W1. Therefore, the ratio would be larger than 1.05-1.5).
As cited from MPEP 2144.05, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (The prior art taught carbon monoxide concentrations of "about 1-5%" while the claim was limited to "more than 5%." The court held that "about 1-5%" allowed for concentrations slightly above 5% thus the ranges overlapped.); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997) (Claim reciting thickness of a protective layer as falling within a range of "50 to 100 Angstroms" considered prima facie obvious in view of prior art reference teaching that "for suitable protection, the thickness of the protective layer should be not less than about 10 nm [i.e., 100 Angstroms]." The court stated that "by stating that ‘suitable protection’ is provided if the protective layer is ‘about’ 100 Angstroms thick, [the prior art reference] directly teaches the use of a thickness within [applicant’s] claimed range.").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have Liaw choose the higher range for the ratio between the third and fourth width because increasing the width difference between the pull-down transistor and the pull-up transistor because having a larger pull-down transistor can increase the current available which can improve the noise margin of the cell, helping to maintain data integrity.
Claim(s) 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 20230032523) in view of Chou et al. (US 20230380130 A1).
Regarding claim 21, Liaw teaches A memory device, comprising:
a first memory cell including a first active region for transistors of a first conductivity type, a second active region for transistors of a second conductivity type opposite to the first conductivity type (Fig 7 shows a first memory cell, 152, has a first active region, 215J and a second active region, 215I. Paragraph 0022 describes that P-wells are configured for n-type transistors and the N-wells are designed for P-type transistors. As Fig 7 shows 215J in the P-type well and 215I in the N-type well, the first active region, 215J, contains n-type transistors, and the second active region, 215I contains p-type transistors, making them active regions with opposite conductivity types), and a first gate structure engaging a channel region of the first active region (Paragraph 0018 states that the gate stacks, 240, engage with all of the channel regions. Fig 7 shows a first gate stack in the first active region, 215J), wherein the first active region has a first width (The first active region, 215J, has the first width, W5), the second active region has a second width smaller than the first width (The second active region, 215I, has the second width W6. Fig 7 shows that the second width, W6, is smaller than the first width, W5), and the first gate structure has a first gate width (Paragraph 0019 describes the gate channel having a width); and
a second memory cell including a third active region for transistors of the first conductivity type, a fourth active region for transistors of the second conductivity type (Fig 3 shows a second memory cell, 102, has a third active region, 215E and a fourth active region, 215D. Paragraph 0022 describes that P-wells are configured for n-type transistors and the N-wells are designed for P-type transistors. As Fig 3 shows 215E in the P-type well and 215D in the N-type well, the first active region, 215E, contains n-type transistors, and the second active region, 215D contains p-type transistors. Therefore, the third active region has the same conductivity type as the first active region, and the fourth active region has the same conductivity type as the second active region), and a second gate structure engaging a channel region of the third active region (Paragraph 0018 states that the gate stacks, 240, engages with all of the channel regions. Fig 3 shows that the third active region, 215J containing gate stacks, 240), wherein the third active region has a third width (The third active region 215E has the third width, W2), the fourth active region has a fourth width smaller than the third width (The fourth active region, 215D, has the fourth width, W3. Fig 3 shows that the third width, W2, is larger than the fourth width, W3), and the second gate structure has a second gate width (Paragraph 0019 describes the gate channel having a width. Fig 3 shows that the third active region, 215E, contains gate stacks, 240),
wherein the first width is larger than the third width (Paragraph 0041 states that the first width, W5, is greater than the third width, W2),
Liaw does not teach the second gate width is larger than the first gate width.
Chou et al. teaches the first gate having a first gate width (Paragraph 0050 states that one gate has one dimension, L2) , the second gate having a second gate width (Paragraph 0050 states that the other gate has another dimension, L1), wherein the second gate width is larger than the first gate width (Paragraph 0050 states that L1 is greater than L2, the ratio of L1 to L2 being from 1.1 to 1.5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Liaw to have the second gate width larger than the first gate width, as taught in Chou et al., because varying gate widths in a memory device allows for the compensation of tailoring different channel widths ensuring better electrical uniformity across the device.
Regarding claim 22, Liaw, as modified, teaches the first conductivity type is n-type and the second conductivity type is p-type (Paragraph 0022 describes that P-wells are configured for n-type transistors and the N-wells are designed for P-type transistors. As Figs 3 and 7 shows 215E and 215J, which correspond to the first and third active region, are in the P-type well and both 215D and 215I, which correspond to the second and fourth active region, are in the N-type well. Therefore, the first a conductivity type is n-type and the second conductivity type p-type).
Regarding claim 23, Liaw, as modified, teaches a ratio of the second gate width over the first gate width ranging from about 1 to about 1.5 (Paragraph 0050 of Chou, which has already been used to modify the size difference between first gate width over the second gate width, states that the ratio of the second gate width, L1, is larger than the second gate, L2, by a ratio of 1.1 to 1.5, which fits within the range of about 1 to 1.5).
Regarding claim 24, Liaw, as modified, teaches the first memory cell is in a level-1 cache, and the second memory cell is in a level-2 cache (Because Liaw, as modified in claim 21 above, shares the same structure within the claimed structure of claim 21, the first memory cell would be able to function in a level-1 cache and the second memory cell would be able to function in a level-2 cache. The last sentence of paragraph 1 also shows that these levels are well known in the art).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pao et al. (US 20230046028 A1), Huang et al. (US 20230403837), Liaw (US 20220328499 A1) share a similar structure to the application, shows a plurality of memory cells in which contains active regions that contain pull-down (N-type) and pull-up transistors (P-type) transistors with the active regions being different widths from each other.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLOTTE ELIZABETH HARBOTTLE whose telephone number is (571)270-0644. The examiner can normally be reached Monday-Friday 7:30-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.E.H./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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