DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 1, the claim recites, “wherein a column position of an edge of each of the strip-shaped active regions in one row is laterally shifted by a shift distance relative to a column position of a respective edge of each of the strip-shaped active regions in an adjacent row,” which is indefinite as it is not clear which edge the limitation refers to either the leading edge or the trailing edge and hence the metes and bounds of the lateral shift are unclear.
Claims 2-15 depend upon claim 1 and do not rectify the problem therefore, they are also rejected.
Regarding claim 9, the claim recites, “shift distance relative to the column position..”. However, this language is unclear because the shift distance is a distance measured between two column positions, such as between a column position of an edge of a strip-shaped active region in one row and a column position of a respective edge of a strip-shaped active region in an adjacent row not relative to a single column position.
In particular, it is unclear whether the recited column position refers to the column position of an edge of a strip-shaped active region in one row or the column position of a respective edge of a strip-shaped active region in an adjacent row. Since the claim does not clearly define the reference column position for measuring the shift distance the metes and bounds of the claimed shift distance cannot be determined with reasonable certainty.
Claims 11 and 13 depend upon claim 9 and do not rectify the problem therefore, they are also rejected.
Regarding claim 10, the claim recites, “shift distance relative to the column position” which is unclear because the shift distance is measured between two column positions not relative to a single column position.
Further, the claim recites a mathematical relationship without clearly reciting the structural boundaries, location or configuration of the capacitor contact landing area. The claim recites the capacitor contact landing area merely as a calculated numerical area.
Regarding claim 11, the claim recites, “the capacitor contact landing area” which is indefinite and lacks antecedent basis.
Further, the claim recites a mathematical relationship without clearly reciting the structural boundaries, location or configuration of the capacitor contact landing area. The claim recites the capacitor contact landing area merely as a calculated numerical area.
Regarding claim 13, the claim recites, “the cell area” which is indefinite and lacks antecedent basis.
Regarding claim 14, the claim recites, “edge of another strip-shaped active region in an adjacent row”, which is indefinite as it is not clear whether the recited edge is a trailing edge, leading edge, a left or right vertical edge, a top or bottom horizontal edge. It is also not clear where this “another strip-shaped active region” is located with respect to the strip-shaped active regions in an adjacent row recited in claim 1.
Regarding claim 15, the claim recites, “adjacent columns” which is indefinite and lacks antecedent basis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ichise et al. (US 2004/0173838 A1; hereafter Ichise).
Regarding claim 1, Ichise teaches a semiconductor device (see e.g., Dynamic Random Access Memory (DRAM) including storage areas of plural memory arrays, Figure 2), comprising:
a semiconductor substrate (see e.g., semiconductor substrate 1, Para [0056], Figure 2);
an isolation feature on the semiconductor substrate (see e.g., device isolation grooves 2, filled with silicon oxide film 4, formed on the semiconductor substrate 1, Para [0056], Figure 2);
a plurality of strip-shaped active regions defined by the isolation feature (see e.g., a plurality of active regions L separated by device isolation grooves 2, Para [0057], Figure 2), wherein a column position of an edge of each of the strip-shaped active regions in one row is laterally shifted by a shift distance relative to a column position of a respective edge of each of the strip-shaped active regions in an adjacent row, (see e.g., in the layout shown in modified Figure 2, the active regions L are arranged in rows such that an edge of each active area segment in one row is laterally shifted relative to a corresponding edge of an active area segment in an adjacent row)
PNG
media_image1.png
664
678
media_image1.png
Greyscale
Modified Figure 2, Ichise
capacitor contacts on both ends of each of the strip-shaped active regions (see e.g., each of the active regions L are formed of two memory cell selecting MISFETs Qs connected in series to a data storing capacitor C. Contact holes 16, filled with polycrystalline silicon film 17, connect the data storing capacitors C with the memory cell selecting MISFETs Qs and are formed at opposite end portions of each active region L, Paras [0060], [0075], Figure 2).
Ichise does not explicitly teach
“the shift distance is one to two times a width of the strip-shaped active regions;”
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
While Ichise discloses lateral shifting of active regions to create memory layout, Ichise does not explicitly quantify the shift distance as being one to two times a width of the active regions. However, selecting the amount of lateral shift to fall within the claimed range represents a matter of routine DRAM layout optimization. The amount of lateral shift impacts the memory cell packing density. Adjusting this variable to achieve an optimal balance between density and electrical isolation is an expected design choice.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to select a shift distance of about one to two times the active region width as it would have been an obvious design choice and routine optimization to balance isolation spacing, contact margin and cell density.
Regarding claim 2, Ichise, as modified in claim 1, does not explicitly teach
“wherein a distance between strip-shaped active regions in adjacent rows is equal to the width of the strip-shaped active regions”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
Ichise discloses a DRAM memory layout including a plurality of active regions L arranged in rows wherein the active regions are defined by device isolation grooves 2 filled with silicon oxide film 4 as shown in Figure 2. Ichise further discloses that the active regions L are arranged in a repeated memory cell layout.
Ichise does not explicitly quantify the distance between active regions in adjacent rows being equal to the width of the active regions. However, the spacing between adjacent rows of active regions and the width of the active regions are known DRAM layout parameters that affect cell density. Adjusting the adjacent row spacing and the width of the active region to achieve an optimal balance between density and electrical isolation is an expected design choice.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to select a distance between active regions in adjacent rows to be equal to the width of the active regions as it would have been an obvious design choice and routine optimization to balance isolation spacing, contact margin and cell density.
Regarding claim 3, Ichise, as modified in claim 1, does not explicitly teach
“wherein a pitch of the strip-shaped active regions in each row is six times the shift distance”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
Ichise discloses a DRAM memory layout including a plurality of active regions L arranged in rows wherein the adjacent rows of active regions are laterally shifted relative to each other as shown in Figure 2. Ichise therefore teaches the general relationship between a pitch of the active regions in a row and a lateral shift distance between corresponding active region edges in adjacent rows.
Ichise does not explicitly quantify the pitch of the active regions in each row as being six times the shift distance. However, the pitch of active regions and the lateral shift distance between adjacent rows are known DRAM layout parameters that affect cell density. Adjusting the pitch to shift ratio to achieve an optimal balance between density and electrical isolation is an expected design choice.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to select a pitch of the active region being six times the shift distance as it would have been an obvious design choice and routine optimization to balance isolation spacing, contact margin and cell density.
Regarding claim 4, Ichise, as modified in claim 1, does not explicitly teach
“wherein a pitch of the strip-shaped active regions in each row is eight to nine times the width of the strip-shaped active regions”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
Ichise discloses that each active region L has a length along the long arm of about 0.75µm and a width along the short arm of about 0.15µm. Ichise also discloses that the spacing between adjoining active regions L is about 0.15µm. Thus, based on Ichise disclosed dimensions, the pitch is about 0.90µm and therefore a pitch to width ratio is about 6.
Ichise does not explicitly teach the pitch of the active regions in each row as being eight to nine times the width of the active regions. However, the width and pitch of active regions are known DRAM layout parameters that affect cell density. Adjusting the pitch to width ratio to achieve an optimal balance between density and electrical isolation is an expected design choice.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to select a pitch of the active region being eight to nine times the width of the active regions as it would have been an obvious design choice and routine optimization to balance isolation spacing, contact margin and cell density.
Regarding claim 5, Ichise, as modified in claim 4, does not explicitly teach
“wherein a pitch of the strip-shaped active regions in each row is seven times the width of the strip-shaped active regions”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
Ichise discloses that each active region L has a length along the long arm of about 0.75µm and a width along the short arm of about 0.15µm. Ichise also discloses that the spacing between adjoining active regions L is about 0.15µm. Thus, based on Ichise disclosed dimensions, the pitch is about 0.90µm and therefore a pitch to width ratio is about 6.
Ichise does not explicitly teach the pitch of the active regions in each row as being seven times the width of the active regions. However, the width and pitch of active regions are known DRAM layout parameters that affect cell density. Adjusting the pitch to width ratio to achieve an optimal balance between density and electrical isolation is an expected design choice.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to select a pitch of the active region being seven times the width of the active regions as it would have been an obvious design choice and routine optimization to balance isolation spacing, contact margin and cell density.
Regarding claim 6, Ichise, as modified in claim 1, does not explicitly teach
“wherein a length of the strip-shaped active regions is six to eight times the width of the strip-shaped active regions”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
Ichise discloses that each active region L has a length along the long arm of about 0.75µm and a width along the short arm of about 0.15µm. Thus, based on Ichise disclosed dimensions, the length of active region is about 5 times the width of active region.
Ichise does not explicitly teach the length of the active regions in each row as being six to eight times the width of the active regions. However, the length and width of active regions are known DRAM layout parameters that affect cell density. Adjusting the length to width ratio to achieve an optimal balance between density and electrical isolation is an expected design choice.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to select a length of the active region being six to eight times the width of the active regions as it would have been an obvious design choice and routine optimization to balance isolation spacing, contact margin and cell density.
Regarding claim 8, Ichise, as modified in claim 1, further teaches
wherein the capacitor contacts comprise doped polycrystalline silicon (see e.g., plugs 17 are formed by depositing a low resistance polycrystal silicon film with n-type impurities into the contact holes 16 which connect the data storing capacitors C with the memory cell selecting MISFETs Qs, Paras [0075], [0076], Figures 2 and 3).
Regarding claim 9, Ichise, as modified in claim 1, does not explicitly teach
“wherein the shift distance relative to the column position is one to two times the width of the strip-shaped active regions”.
Ichise does not explicitly teach
“wherein the shift distance relative to the column position is one to two times a width of the strip-shaped active regions;”
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
While Ichise discloses lateral shifting of active regions to create memory layout, Ichise does not explicitly quantify the shift distance as being one to two times a width of the active regions. However, selecting the amount of lateral shift to fall within the claimed range represents a matter of routine DRAM layout optimization. The amount of lateral shift impacts the memory cell packing density. Adjusting this variable to achieve an optimal balance between density and electrical isolation is an expected design choice.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to select a shift distance of about one to two times the active region width as it would have been an obvious design choice and routine optimization to balance isolation spacing, contact margin and cell density.
Regarding claim 10, Ichise, as modified in claim 1, further teaches
wherein the shift distance relative to the column position times the width of the strip-shaped active regions defines a capacitor contact landing area (see e.g., plugs 17 are formed at the corners of the active regions L, Figure 2).
Regarding claim 11, Ichise, as modified in claim 9, further teaches
wherein the capacitor contact landing area is one to two times the square of the width of the strip-shaped active regions (see e.g., plugs 17 are formed at the corners of the active regions L, Figure 2).
Regarding claim 12, Ichise, as modified in claim 1, further teaches
wherein a pitch of the strip-shaped active regions in each row times the width of the strip-shaped active regions defines a cell area (see e.g., the DRAM comprises an array of memory cells including active regions L isolated from each other by device isolation grooves 2 filled with silicon oxide film 4, Paras [0057], [0058], Figure 2).
Regarding claim 13, Ichise, as modified in claim 11, does not explicitly teach
“wherein the cell area is eight to nine times the square of the width of the strip-shaped active regions”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
Ichise discloses a DRAM memory layout including a plurality of active regions L (memory cells) arranged in rows wherein the active regions are defined by device isolation grooves 2 filled with silicon oxide film 4 as shown in Figure 2. Ichise further discloses that the active regions L are arranged in a repeated memory cell layout.
Ichise does not explicitly quantify the cell area being eight to nine times the square of the width of the active rgeions. However, the cell area is a known DRAM layout parameter that affects cell density. Adjusting the cell area to achieve an optimal balance between density and electrical isolation is an expected design choice.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to select a cell area being eight to nine times the square of the width of the active regions as it would have been an obvious design choice and routine optimization to balance isolation spacing, contact margin and cell density.
Regarding claim 15, Ichise, as modified in claim 1, further teaches
wherein a distance between strip-shaped active regions in adjacent columns is one to two times the width of the strip-shaped active regions (see e.g., the active regions L have a length along the shirt arm equal to the minimum size for example, 0.15µm, which corresponds to the width of the active regions L. The spacing between adjoining active regions L is almost equal to the minimum size for example, 0.15µm, Para [0068], Figure 2).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ichise et al. (US 2004/0173838 A1; hereafter Ichise) in view of Park et al. (US 2014/0327062 A1; hereafter Park).
Regarding claim 7, Ichise, as modified in claim 1, does not explicitly teach
“wherein the capacitor contacts comprise TiN, Cu, W, Al, or a combination thereof”.
In a similar field of endeavor Park teaches
wherein the capacitor contacts comprise TiN, Cu, W, Al, or a combination thereof (see e.g., contact plug 180 may be a storage node contact and may be made of a conductive material for example, at least one of polysilicon, a metal silicide compound, a conductive metal nitride, and/or a metal, Paras [0074], [0139], Figure 4).
Park discloses the use of metal nitrides, such as titanium nitride and metals, such as tungsten for the gate electrode. Because Park expressly mentions these materials it would have been obvious to utilize similar well-known conductive materials for the capacitor contact plugs 180.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Park’s teachings of wherein the capacitor contacts comprise TiN, Cu, W, Al, or a combination thereof in the device of Ichise as these are standard, interchangeable materials in the semiconductor art.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ichise et al. (US 2004/0173838 A1; hereafter Ichise) in view of Liu et al. (US 6352896 B1; hereafter Liu).
Regarding claim 14, Ichise, as modified in claim 1, does not explicitly teach
“wherein the edge of each of the strip-shaped active regions in one row is aligned with an edge of another strip-shaped active region in an adjacent row”.
PNG
media_image2.png
548
947
media_image2.png
Greyscale
Modified Figure 2A, Liu
In a similar field of endeavor Liu teaches
wherein the edge of each of the strip-shaped active regions in one row is aligned with an edge of another strip-shaped active region in an adjacent row (see e.g., as shown in modified Figure 2A the edge of active region 204 in one row is aligned with the edge of another active region in an adjacent row).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Liu’s teachings of wherein the edge of each of the strip-shaped active regions in one row is aligned with an edge of another strip-shaped active region in an adjacent row in the device of Ichise since such a modification would have been a predictable variation of known DRAM active region layout arrangements providing predictable spacing and overlay margins between active regions and contacts.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAKEHA SEHAR whose telephone number is (571)272-4033. The examiner can normally be reached Monday-Thursday 7:00 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using
a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be
obtained from Patent Center. Unpublished application information in Patent Center is available to
registered users. To file and manage patent submissions in Patent Center, visit:
https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more
information about Patent Center and https://www.uspto.gov/patents/docx for information about
filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at
866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service
Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights