DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/12/2024 and 3/13/2026 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12033947. Although the claims at issue are not identical, they are not patentably distinct from each other because applicant merely seeks to broaden the claims by removing limitations, for example, of the interposer in claim 1, and the vertical overlapping of third via structures over a dielectric, which overlaps a bottom via structures, and has a thickness greater than the sum of the first two via structures.
A semiconductor package structure, comprising:
a first bottom electrical connector
first bottom via structures formed over the first bottom electrical connector
a trace of a first redistribution layer structure formed over the first bottom via structures
first via structures formed over the trace of the first redistribution layer structure
a trace of a second redistribution layer structure formed over the first via structures
second via structures formed over the trace of the second redistribution layer structure
a trace of a third redistribution layer structure formed over the second via structures and partially vertically overlapping the trace of the first redistribution layer structure
wherein the trace of the first redistribution layer structure, the trace of the second redistribution layer structure, and the trace of the third redistribution layer structure extend in different directions
A semiconductor package structure, comprising:
a first bottom electrical connector
an interposer formed over the first bottom electrical connector, wherein the interposer comprises
first bottom via structures in contact with the first bottom electrical connector
a first trace of a first redistribution layer structure formed over the first bottom via structures
first via structures formed over the first trace of the first redistribution layer structure
a first trace of a second redistribution layer structure formed over the first via structures
second via structures formed over the first trace of the second redistribution layer structure
a first trace of a third redistribution layer structure formed over the second via structures
third via structures formed over the first trace of the third redistribution layer structure
wherein the first bottom via structures, the first via structures, and the second via structures are separated from each other in a top
wherein one of the third via structures vertically overlaps a portion of a dielectric layer, and the portion of the dielectric layer vertically overlaps one of the first bottom via structures and has a thickness greater than a sum of a thickness of one of the first via structures and a thickness of one of the second via structures
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-5, and 7-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nin et al. (US Publication No. 2012/0267776).
Regarding claim 1, Nin discloses a semiconductor package structure, comprising:
a first bottom electrical connector (604)
first bottom via structures (402a) formed over the first bottom electrical connector (604)
a trace (404a) of a first redistribution layer structure formed over the first bottom via structures (402a)
first via structures (402a) formed over the trace of the first redistribution layer structure
a trace (below 412a) of a second redistribution layer structure formed over the first via structures (402a)
second via structures (402a) formed over the trace of the second redistribution layer structure
a trace (404c) of a third redistribution layer structure formed over the second via structures (402a) and partially vertically overlapping the trace of the first redistribution layer structure
wherein the trace of the first redistribution layer structure, the trace of the second redistribution layer structure, and the trace of the third redistribution layer structure extend in different directions (Figures 4-5)
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Regarding claim 3, Nin discloses a trace (404d) of a fourth redistribution layer structure formed over the trace of the third redistribution layer structure, wherein the trace of the fourth redistribution layer structure, the trace of the second redistribution layer structure, and the trace of the third redistribution layer structure extend in different directions (Figures 4-5).
Regarding claim 4, Nin discloses an extending direction of the trace (404a) of the first redistribution layer structure and an extending direction of the trace (404d) of the fourth redistribution layer structure are substantially the same (Figure 7).
Regarding claim 5, Nin discloses the first bottom via structures (402a), the first via structures (402a), and the second via structures (402a) are separated from each other in a top view.
Regarding claim 7, Nin discloses third via structures (412c) formed over the trace of the third redistribution layer structure and vertically overlapping the first bottom via structures (402a) (Figures 4-5).
Regarding claim 8, Nin does not disclose a semiconductor package structure, comprising:
a first conductive unit comprising:
a first bottom via layer (402a)
a first redistribution layer (404a) structure comprising a first trace formed over the first bottom via layer (402a)
a first middle via layer (402b) formed over the first redistribution layer structure
a second redistribution layer (404b) structure comprising a second trace formed over the first middle via layer (402b)
a third redistribution layer structure (404c) comprising a third trace formed over the second redistribution layer structures (404b)
a second conductive unit formed over the first conductive unit, wherein the second conductive unit comprises:
a second bottom via layer (402c) vertically overlapping the first bottom via layer
a fourth redistribution layer structure comprising a fourth trace (404c) formed over the second bottom via layer
wherein the first trace (404a) of the first redistribution layer structure, the second trace (404b) of the second redistribution layer structure, and the third trace of the third redistribution layer structure extend in different directions in a top view (Figures 4-5)
a distance between the third trace of the third redistribution layer structure and the first trace (404a) of the first redistribution layer structure is greater than a distance between the third trace (404c) of the third redistribution layer structure and the fourth trace of the fourth redistribution layer structure in a cross-sectional view (Figures 4-5)
Regarding claim 9, Nin discloses an extending direction of the fourth trace (404d) of the fourth redistribution layer structure and an extending direction of the third trace (404c) of the third redistribution layer structure are substantially the same (Figure 7).
Regarding claim 10, Nin discloses a first bottom electrical connector (604a) electrically connected to a first via structure of the first bottom via layer; and a second bottom electrical connector (604b) electrically connected to a second via structure of the first bottom via layer, wherein a width of the second via structure is greater than a width of the first via structure (Figure 7).
Regarding claim 11, Nin discloses a height of the second bottom electrical connector is greater than a height of the first bottom electrical connector (Figure 9).
Regarding claim 12, Nin discloses a substrate (600) electrically connected to the second bottom electrical connector (604) and comprising a recess; and a device electrically (602) connected to the first bottom electrical connector and disposed in the recess.
Regarding claim 13, Nin discloses an underfill layer (between 604) extending into the recess and surrounding the first bottom electrical connector and the second bottom electrical connector (Figure 8).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nin (US Publication No. 2012/0267776) in view of Jang et al. (US Publication No. 2021/0233897).
Regarding claim 6, Nin discloses the limitations as discussed in the rejection of claim 5 above. Nin does not disclose a distance L between a center of one of the first bottom via structures and a center of one of the first via structures is greater than about 3 μm. However, Jang discloses a distance L between a center of one of the first bottom via structures and a center of one of the first via structures is greater than about 3 μm (paragraph 31). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the L distance to be within this range to maintain density while minimizing unwanted capacitance, therefore improving electrical characteristics (paragraph 5).
Claims 2 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nin (US Publication No. 2012/0267776) in view of Zhang et al. (US Publication No. 2014/0268614).
Regarding claim 2, Nin discloses the limitations as discussed in the rejection of claim 1 above. Nin does not disclose an angle between an extending direction of the trace of the first redistribution layer structure and an extending direction of the trace of the second redistribution layer structure is about 30°. However, Zhang discloses an angle between different extending direction being above 30° (Figure 2). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the angle of each extending direction vertex to be different, as taught by Zhang, since it can improve packing density of the connections (paragraph 25).
Regarding claim 14, Nin discloses a semiconductor package structure, comprising:
a first trace (402a) of a first redistribution layer structure having a first extending direction
a second trace (below 412a) of a second redistribution layer structure over the first trace of the first redistribution layer structure and having a second extending direction
a third trace (404c) of a third redistribution layer structure over the second trace of the second redistribution layer structure and having a third extending direction
Nin does not disclose a first angle between the first extending direction and the second extending direction is different from a second angle between the first extending direction and the third extending direction. However, Zhang discloses an angle between different extending direction being different (Figure 2). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the angle of each extending direction vertex to be different, as taught by Zhang, since it can improve packing density of the connections (paragraph 25).
Regarding claim 15, Zhang disclose the first angle between the first extending direction and the second extending direction is greater than the second angle between the first extending direction and the third extending direction (paragraph 25; Figure 2). As discussed above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Nin in view of Zhang.
Regarding claim 16, Zhang discloses the first angle between the first extending direction and the second extending direction is about 120° (paragraph 27; Figure 2). As discussed above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Nin in view of Zhang.
Regarding claim 17, Nin discloses a fourth trace of a fourth redistribution layer structure over the third trace of the third redistribution layer structure and having the first extending direction (Figure 4).
Regarding claim 18, Nin discloses a fifth trace of a fifth redistribution layer structure over the fourth trace of the fourth redistribution layer structure and having the second extending direction; and a sixth trace of a sixth redistribution layer structure over the fifth trace of the fifth redistribution layer structure and having the third extending direction (Figure 4).
Regarding claim 19, Nin discloses the sixth trace of the sixth redistribution layer structure partially vertically overlaps the first trace of the first redistribution layer structure (Figure 4).
Regarding claim 20, Zhang discloses the first trace of the first redistribution layer structure, the second trace of the second redistribution layer structure, the third trace of the third redistribution layer structure, the fourth trace of the fourth redistribution layer structure, the fifth trace of the fifth redistribution layer structure, and the sixth trace of the sixth redistribution layer structure are arranged in a shape of a hexagon (Figure 2). As discussed above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Nin in view of Zhang.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
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/N.R.P/ 8/31/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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