Prosecution Insights
Last updated: April 19, 2026
Application No. 18/740,889

METHOD FOR FORMING A SEMICONDUCTOR PACKAGE WITH STRESS REDUCTION DESIGN

Final Rejection §103
Filed
Jun 12, 2024
Examiner
KHALIFA, MOATAZ
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
2 (Final)
94%
Grant Probability
Favorable
3-4
OA Rounds
3y 4m
To Grant
88%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allow Rate
50 granted / 53 resolved
+26.3% vs TC avg
Minimal -6% lift
Without
With
+-6.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
45 currently pending
Career history
98
Total Applications
across all art units

Statute-Specific Performance

§103
70.6%
+30.6% vs TC avg
§102
17.5%
-22.5% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 53 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Remarks The 01/27/2026 amendments of claims 1-2, 10-11 and 16-18 have been noted and entered. The 01/27/2026 cancellation of claims 7-9 and 14-15 has been noted and entered. The 01/27/2026 addition of new claims 21-25 has been noted and entered. Response to Arguments Applicant’s arguments, see Remarks pages 7-8, filed 01/27/2026, with respect to the objections to claim 8 for minor informalities have been fully considered and are persuasive in light of the newly added amendments. Thus, the previous objections of record have been withdrawn. Applicant’s arguments, see Remarks pages 7-9, filed 01/27/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 102 and 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Wang et al, US 20200350261 A1 (Wang). New Grounds of Rejection New grounds of rejection, prior art reference Wang et al, US 20200350261 A1 (Wang), appears below. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3-6, 10-13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Isobe, US 20170162404 A1 (Isobe) in view of Wang et al, US 20200350261 A1 (Wang). Regarding claim 1; Isobe teaches a method for forming a semiconductor package, comprising: mounting a semiconductor device (11) on a surface of a package substrate (12); forming an underfill element (31) between the semiconductor device (11) and the surface of the package substrate (12), wherein the underfill (31) element comprises a fillet portion (see annotated Fig (10) of Isobe shared in this OA for convenience) that extends laterally beyond a periphery of the semiconductor device (11) and is formed along the periphery of the semiconductor device (11); and forming a plurality of grooves (111) in the fillet portion (see annotated Fig (10) of Isobe shared in this OA for convenience). PNG media_image1.png 777 595 media_image1.png Greyscale Isobe does not teach wherein the grooves formed near the corners of the semiconductor device and away from the sides of the semiconductor device in a plan view. However, Wang teaches wherein the grooves (34) formed near the corners of the semiconductor device (21) and away from the sides of the semiconductor device (21) in a plan view (see Figures (5A)-(5E) of Wang shared in this OA). Isobe and Wang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Isobe by constructing the grooves near the corners of the device and away from the sides as disclosed in Wang to reduce the mechanical stress on the chip and its packaging given that the corners are the areas that experience the highest levels of mechanical stress leading to a more reliable device. PNG media_image2.png 879 664 media_image2.png Greyscale Regarding claim 3; Isobe in view of Wang teaches all the limitations of claim 1. Further, Isobe teaches wherein each of the grooves (111) is spaced apart from the periphery of the semiconductor device (11). Regarding claim 4; Isobe in view of Wang teaches all the limitations of claim 1. Further, Isobe teaches wherein each of the grooves (111) is formed to extend from an outside surface of the fillet (see annotated Fig (10) of Isobe shared in this OA for convenience) portion toward the surface of the package substrate (12), but does not reach the surface of the package substrate (12). Regarding claim 5; Isobe in view of Wang teaches all the limitations of claim 4. However, Isobe teaches wherein each of the grooves is formed to extend in a direction perpendicular to the surface of the package substrate. Wang teaches wherein each of the grooves (34) is formed to extend in a direction perpendicular to the surface of the package substrate (12) (see Fig (5A) of Isobe reproduced in this OA for convenience). Isobe and Wang are considered analogous art. Thus, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the incident application, to modify Isobe by forming the grooves to extend in a direction that is perpendicular to the surface of the package substrate to enhance the ability of the grooves to absorb the stress generated on the device leading to a more reliable device. Regarding claim 6; Isobe in view of Wang teaches all the limitations of claim 4. Further, Isobe teaches wherein each of the grooves (111) is formed to extend in a direction inclined relative to the surface of the package substrate (12) (see Fig (10) of Isobe reproduced in this OA for convenience). Regarding claim 10; Isobe in view of Wang teaches all the limitations of claim 1. Further, Isobe teaches wherein the grooves (111) comprise a group of grooves (111) arranged in a width direction of the fillet portion (see annotated Fig (10) of Isobe shared in this OA for convenience) perpendicular to the periphery of the semiconductor device (11). Regarding claim 11; Isobe teaches a method for forming a semiconductor package, comprising: mounting a semiconductor device (11) on a surface of a package substrate (12); forming an underfill element (31) between the semiconductor device (11) and the surface of the package substrate (12), wherein the underfill element (31) comprises a fillet portion (see annotated Fig (10) of Isobe shared in this OA for convenience) that extends laterally beyond a periphery of the semiconductor device (11) and is formed along the periphery of the semiconductor device (11); and forming a plurality of separated grooves (111) in the fillet portion (see annotated Fig (10) of Isobe shared in this OA for convenience), wherein the plurality of separated grooves (111) wherein the semiconductor device (11) comprises a plurality of corners and a plurality of sides. Isobe does not teach the separated grooves are arranged to correspond to some or all of the corners and are located away from the sides in a plan view. However, Wang teaches the separated grooves (34) are arranged to correspond to some or all of the corners and are located away from the sides in a plan view (see Figures (5A) – (5E) of Wang shared in this OA). Isobe and Wang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Isobe by constructing the grooves near the corners of the device and away from the sides as disclosed in Wang to reduce the mechanical stress on the chip and its packaging given that the corners are the areas that experience the highest levels of mechanical stress thus leading to a more reliable device. Regarding claim 12; Isobe in view of Wang teaches all the limitations of claim 11. Further, Isobe teaches wherein the fillet portion (see annotated Fig (10) of Isobe shared in this OA for convenience) has an inner edge adjacent to the periphery of the semiconductor device (11) and an outer edge opposite to the inner edge, and wherein each groove (111) of the plurality of separated grooves (111) is spaced apart from the inner edge and the outer edge of the fillet portion (see annotated Fig (10) of Isobe shared in this OA for convenience). Regarding claim 13; Isobe in view of Wang teaches all the limitations of claim 11. Further, Isobe teaches wherein the fillet portion (see annotated Fig (10) of Isobe shared in this OA for convenience) has an outside surface that slopes up from the surface of the package substrate (12) to the periphery of the semiconductor device (11), and wherein each groove (111) of the plurality of separated grooves (111) is formed to extend from an outside surface of the fillet portion (see annotated Fig (10) of Isobe shared in this OA for convenience) toward the surface of the package substrate (12). Regarding claim 16; Isobe further teaches in the embodiment of figure 4 wherein the semiconductor device comprises two dies ((11-1) and (11-2)) arranged side by side, and a gap is formed between the two dies ((11-1) and (11-2)), and wherein the method further comprises forming a plurality of additional grooves (111) arranged corresponding to the gap in the plan view (see Fig (4) of Isobe shared in this OA for convenience). Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Isobe’s embodiment of figure 10 by using two dies as disclosed in figure 4 since it was known in the art to fabricate multiple chips at the same time as evidenced by figures 4-5 and since it has been held that mere duplication of part has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP §2144.04 VI B. PNG media_image3.png 579 436 media_image3.png Greyscale Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Isobe, US 20170162404 A1 (Isobe) in view of Wang et al, US 20200350261 A1 (Wang) in further view of Yeh et al, US 20170221788 A1 (Yeh) Regarding claim 2; Isobe in view of Wang teaches all the limitations of claim 1. However, Isobe in view of Wang does not teach wherein the one or more grooves are formed by laser cutting Yeh teaches wherein the one or more grooves are formed by laser cutting (see paragraph [0028] of the specifications of Yeh: “ [0028] The groove 124 may be formed by a laser ablation process that uses, for example, an EO Laser Ablation-BMC502PI offered by EO Technics Co, Ltd. having a laser power setting of approximately 3.7 W plus or minus 0.3 W. In an embodiment the laser ablation process may be performed by irradiating or ablating the molding compound 112 with a series of laser pulses to form the grooves 124”). Isobe in view of Wang and Yeh are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Isobe in view of Wang by using a laser to form the grooves as disclosed in Yeh to make the production process of the device easier and more efficient. PNG media_image4.png 724 1009 media_image4.png Greyscale PNG media_image5.png 734 993 media_image5.png Greyscale Claims 17-22 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Isobe, US 20170162404 A1 (Isobe) in view of Yeh et al, US 20170221788 A1 (Yeh) Regarding claim 17; Isobe teaches a method for forming a semiconductor package, comprising: mounting a semiconductor device (11) on a surface of a package substrate (12); forming an underfill element (31) between the semiconductor device (11) and the surface of the package substrate (12), wherein the underfill element (31) comprises a fillet portion (see annotated Fig (10) of Isobe shared in this OA for convenience) that extends laterally beyond a periphery of the semiconductor device (11) and is formed along the periphery of the semiconductor device (11); and forming at least one groove (111) in the fillet portion(see annotated Fig (10) of Isobe shared in this OA for convenience), wherein the semiconductor device(11) comprises a plurality of sides and a plurality of corners and the at least one groove (111) is arranged to correspond to at least one corner of the plurality of corners of the semiconductor device (11) in a plan view. However, Isobe does not teach the at least one groove is located away from the corners of the semiconductor device, and wherein a shape of each groove of the at least one groove matches a shape of the corresponding corner of the plurality of corners in the plan view. Yeh teaches the at least one groove (124) is located away from the corners of the semiconductor device (104) (see Figures (1C) and (1D)), wherein a shape of each groove (124) of the at least one groove (124) matches a shape of the corresponding corner of the plurality of corners (the corners of (14)) in the plan view (see Figures (1C) and (1D)). Isobe and Yeh are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Isobe by using the matching shapes of the grooves and the corners of the device as disclosed in Yeh to improve their ability to protect the device from mechanical stress leading to a better performing device. Regarding claim 18; Isobe in view of Yeh discloses all the limitations of claim 17. However, Isobe does not teach wherein each groove of the at least one groove is L-shaped in the plan view. Yeh teaches wherein each groove (124) of the at least one groove is L-shaped in the plan view. Isobe and Yeh are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Isobe by using the L-shaped grooves as disclosed in Yeh to improve their ability to protect the device from mechanical stress leading to a better performing device. Regarding claim 19; Isobe in view of Yeh discloses all the limitations of claim 17. Further, Isobe teaches wherein the at least one groove (111) is laterally spaced apart from the periphery of the semiconductor device (11). Regarding claim 20; Isobe in view of Yeh teaches all the limitations of claim 17. Further, Isobe teaches wherein a bottom surface of the at least one groove (111) is spaced apart from the surface of the package substrate (12). Regarding claim 21; Isobe in view of Yeh teaches all the limitations of claim 17. Isobe does not teach wherein each of the at least one groove comprises a first extension part, a second extension part, and a connection part connected between the first extension part and the second extension part, wherein the first extension part and the second extension part are parallel to two adjacent sides of the semiconductor device, respectively. However, Yeh teaches wherein each of the at least one groove (124) comprises a first extension part (First Extension Part – see annotated Fig (1D) of Yeh shared in this OA), a second extension part (Second Extension Part – see annotated Fig (1D) of Yeh shared in this OA), and a connection part (Connection Part – see annotated Fig (1D) of Yeh shared in this OA) connected between the first extension part and the second extension part (First and Second Extension Parts – see annotated Fig (1D) of Yeh shared in this OA), wherein the first extension part and the second extension part (First and Second Extension Parts – see annotated Fig (1D) of Yeh shared in this OA) are parallel to two adjacent sides of the semiconductor device (104), respectively. Isobe and Yeh are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Isobe by constructing the grooves having a first extension part and a second extension part and a connection part as disclosed in Yeh to improve their ability to protect the device from mechanical stress leading to a better performing device. PNG media_image6.png 791 922 media_image6.png Greyscale Regarding claim 22; Isobe in view of Yeh teaches all the limitations of claim 21. Isobe does not teach wherein the connection part is L- shaped in the plan view. Yeh teaches wherein the connection part (Connection Part – see annotated Fig (1D) of Yeh shared in this OA) is L- shaped in the plan view. Isobe and Yeh are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Isobe by using the L-shaped connection part as disclosed in Yeh to improve their ability to protect the device from mechanical stress leading to a better performing device. Regarding claim 25; Isobe in view of Yeh teaches all the limitations of claim 17. However, Isobe does not teach wherein the one or more grooves are formed by laser cutting Yeh teaches wherein the one or more grooves are formed by laser cutting (see paragraph [0028] of the specifications of Yeh: “ [0028] The groove 124 may be formed by a laser ablation process that uses, for example, an EO Laser Ablation-BMC502PI offered by EO Technics Co, Ltd. having a laser power setting of approximately 3.7 W plus or minus 0.3 W. In an embodiment the laser ablation process may be performed by irradiating or ablating the molding compound 112 with a series of laser pulses to form the grooves 124”). Isobe and Yeh are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Isobe by using a laser to form the grooves as disclosed in Yeh to make the production process of the device easier and more efficient. Claims 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Isobe, US 20170162404 A1 (Isobe) in view of Yeh et al, US 20170221788 A1 (Yeh) in further view of Wang et al, US 20200350261 A1 (Wang). Regarding claim 23; Isobe in view of Yeh teaches all the limitations of claim 22. Isobe in view of Yeh do not teach wherein the first extension part, the second extension part, and the connection part have a uniform width. However, Wang teaches wherein the first extension part (First Extension Part – see annotated Fig (5A) of Wang shared in this OA), the second extension part (Second Extension Part – see annotated Fig (5A) of Wang shared in this OA), and the connection part (Connection Part – see annotated Fig (5A) of Wang shared in this OA) have a uniform width. Isobe in view of Yeh and Wang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Isobe in view of Yeh by making the first extension and part and the second extension part and the connection part have a uniform width as disclosed in Wang to simplify the device construction process leading to a more efficient production process. PNG media_image7.png 558 1123 media_image7.png Greyscale Regarding claim 24; Isobe in view of Yeh teaches all the limitations of claim 17. However, Isobe in view of Yeh do not teach wherein forming at least one groove comprises forming a group of grooves arranged in a width direction of the fillet portion perpendicular to the periphery of the semiconductor device and corresponding to the at least one corner of the semiconductor device. Wang teaches wherein forming at least one groove (34) comprises forming a group of grooves (34) arranged in a width direction of the fillet portion perpendicular to the periphery of the semiconductor device (21) and corresponding to the at least one corner of the semiconductor device (21) (see Fig (5A) of Wang). Isobe in view of Yeh and Wang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to one having ordinary skill in the art, to modify Isobe in view of Yeh by constructing a group of grooves arranged in a width direction and corresponding to at least one corner of the semiconductor device as disclosed in Wang to enhance the ability of the grooves to reduce the stress generated on the chip and thus create a more reliable device. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /M.K./Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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Prosecution Timeline

Jun 12, 2024
Application Filed
Oct 24, 2025
Non-Final Rejection — §103
Jan 15, 2026
Examiner Interview Summary
Jan 15, 2026
Applicant Interview (Telephonic)
Jan 27, 2026
Response Filed
Feb 26, 2026
Final Rejection — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
94%
Grant Probability
88%
With Interview (-6.4%)
3y 4m
Median Time to Grant
Moderate
PTA Risk
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