DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The IDS filed on December 03rd, 2025 has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Package structure including heat sink structure having thermal vias and method for manufacturing the same.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-13 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of copending Application No. 18/741,098 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed invention of the instant application is encompassed by the claimed invention of Application No. 18/741,098, see comparison table below.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
1. A package structure, comprising: an electronic device; and a heat sink structure disposed over the electronic device, and comprising: a thermally conductive layer; and a plurality of thermal vias connecting to a second surface of the thermally conductive layer; wherein a first surface of the thermally conductive layer contacts a plurality of pads of the electronic device as to dissipate a heat generated from the electronic device to the thermal vias.
1. A package structure, comprising: an electronic device; and a heat sink structure disposed over the electronic device, and comprising: a thermally conductive layer; a plurality of thermal vias connecting to a second surface of the thermally conductive layer; and a plurality of pads connecting to a first surface of the thermally conductive layer, wherein the plurality of pads are thermally connected to the electronic device so as to dissipate a heat generated from the electronic device to the thermal vias through the thermally conductive layer.
2. The package structure of claim 1, wherein the heat sink structure is attached to the electronic device by hybrid bonding.
2. The package structure of claim 1, wherein the heat sink structure is attached to the electronic device by hybrid bonding.
3. The package structure of claim 1, wherein the thermally conductive layer has a net shape.
. The package structure of claim 1, wherein the thermally conductive layer has a net shape.
4. The package structure of claim 3, wherein the thermally conductive layer includes a plurality of lines crossed with each other to form a plurality of intersection portions.
4. The package structure of claim 3, wherein the thermally conductive layer includes a plurality of lines crossed with each other to form a plurality of intersection portions.
5. The package structure of claim 4, wherein the plurality of thermal vias are connected to the plurality of intersection portions of the thermally conductive layer.
5. The package structure of claim 4, wherein the plurality of thermal vias are connected to the plurality of intersection portions of the thermally conductive layer.
6. The package structure of claim 1, wherein the heat sink structure further comprises: a plurality of conductive elements covering the plurality of thermal vias; and a protection material encapsulating the plurality of conductive elements.
6. The package structure of claim 1, wherein the heat sink structure further comprises a protection material encapsulating the plurality of thermal vias.
7. The package structure of claim 1, wherein a lateral surface of the heat sink structure is substantially aligned with a lateral surface of the electronic device.
7. The package structure of claim 1, wherein a lateral surface of the heat sink structure is substantially aligned with a lateral surface of the electronic device.
8. The package structure of claim 1, wherein the electronic device comprises: a first semiconductor chip; a second semiconductor chip stacked on and electrically connected to the first semiconductor chip; a third semiconductor chip stacked on and electrically connected to the second semiconductor chip; a fourth semiconductor chip stacked on and electrically connected to the third semiconductor chip; and an encapsulant encapsulating the first semiconductor chip, the second semiconductor chip, the third semiconductor chip and the fourth semiconductor chip.
8. The package structure of claim 1, wherein the electronic device comprises: a first semiconductor chip; a second semiconductor chip stacked on and electrically connected to the first semiconductor chip; a third semiconductor chip stacked on and electrically connected to the second semiconductor chip; a fourth semiconductor chip stacked on and electrically connected to the third semiconductor chip; and an encapsulant encapsulating the first semiconductor chip, the second semiconductor chip, the third semiconductor chip and the fourth semiconductor chip.
9. A manufacturing method, comprising: providing an electronic device; providing a heat sink structure, wherein the heat sink structure includes a base portion, a plurality of thermal vias disposed in the base portion and a thermally conductive layer embedded in the base portion and connecting to the plurality of thermal vias; and thermally connecting the heat sink structure to the electronic device, wherein the thermally conductive layer is disposed between the plurality of thermal vias and the electronic device.
9. A manufacturing method, comprising: providing an electronic device; providing a heat sink structure, wherein the heat sink structure includes a base portion, a plurality of thermal vias disposed in the base portion and a thermally conductive layer connecting the plurality of thermal vias; and thermally connecting the heat sink structure to the electronic device, wherein the thermally conductive layer is disposed between the base portion and the electronic device.
10. The method of claim 9, wherein the thermally conductive layer directly contacts the electronic device.
10. The method of claim 9, wherein the plurality of thermal vias connect to a second surface of the thermally conductive layer, and the heat sink structure includes a plurality of pads connecting to a first surface of the thermally conductive layer, wherein the step of thermally connecting the heat sink structure to the electronic device is thermally connecting the plurality of pads to the electronic device.
11. The method of claim 9, wherein the step of thermally connecting the heat sink structure to the electronic device is attaching the heat sink structure to the electronic device by hybrid bonding.
11. The method of claim 9, wherein the step of thermally connecting the heat sink structure to the electronic device is attaching the heat sink structure to the electronic device by hybrid bonding.
12. The method of claim 9, wherein the step of providing the heat sink structure includes: providing the base portion; forming a recess portion in the base portion; forming a plurality of holes in the recess portion; and forming the plurality of thermal vias in the plurality of holes and forming the thermally conductive layer in the recess portion.
12. The method of claim 9, wherein the step of providing the heat sink structure includes: providing the base portion; forming the plurality of thermal vias in the base portion; and forming the thermally conductive layer on the base portion to connect the plurality of thermal vias.
13. The method of claim 9, further comprising: thinning the base portion to expose the plurality of thermal vias; forming a plurality of conductive elements to cover the plurality of thermal vias; and forming a protection material to encapsulate the plurality of conductive elements.
13. The method of claim 9, further comprising: thinning the base portion to expose the plurality of thermal vias.
Claims 1-8 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 18/670,912 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed invention of the present application is encompassed by the claimed invention of Application No. 18/670,912, see comparison table below.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
1. A package structure, comprising: an electronic device; and a heat sink structure disposed over the electronic device, and comprising: a thermally conductive layer; and a plurality of thermal vias connecting to a second surface of the thermally conductive layer; wherein a first surface of the thermally conductive layer contacts a plurality of pads of the electronic device as to dissipate a heat generated from the electronic device to the thermal vias.
1. A package structure, comprising: an electronic device; and a heat sink structure disposed over the electronic device, and comprising: a base portion; a plurality of thermal vias extending through the base portion; and a thermally conductive layer disposed between the base portion and the electronic device, wherein the plurality of thermal vias are thermally connected to the electronic device through the thermally conductive layer so as to dissipate a heat generated from the electronic device.
9. The package structure of claim 8, wherein the heat sink structure further comprises a plurality of pads connecting to the thermally conductive layer and embedded in the dielectric structure, wherein the thermally conductive layer is thermally connected to the electronic device through the plurality of pads.
2. The package structure of claim 1, wherein the heat sink structure is attached to the electronic device by hybrid bonding.
2. The package structure of claim 1, wherein the heat sink structure is attached to the electronic device by hybrid bonding.
3. The package structure of claim 1, wherein the thermally conductive layer has a net shape.
3. The package structure of claim 1, wherein the thermally conductive layer has a net shape.
4. The package structure of claim 3, wherein the thermally conductive layer includes a plurality of lines crossed with each other to form a plurality of intersection portions.
4. The package structure of claim 3, wherein the thermally conductive layer includes a plurality of lines crossed with each other to form a plurality of intersection portions.
5. The package structure of claim 4, wherein the plurality of thermal vias are connected to the plurality of intersection portions of the thermally conductive layer.
5. The package structure of claim 4, wherein the plurality of thermal vias are connected to the plurality of intersection portions of the thermally conductive layer.
6. The package structure of claim 1, wherein the heat sink structure further comprises: a plurality of conductive elements covering the plurality of thermal vias; and a protection material encapsulating the plurality of conductive elements.
11. The package structure of claim 1, wherein the heat sink structure further comprises a protection material disposed on a second surface of the base portion, and encapsulating the plurality of thermal vias.
7. The package structure of claim 1, wherein a lateral surface of the heat sink structure is substantially aligned with a lateral surface of the electronic device.
14. The package structure of claim 13, wherein a lateral surface of the base portion of the heat sink structure is substantially aligned with a lateral surface of the encapsulant of the electronic device.
8. The package structure of claim 1, wherein the electronic device comprises: a first semiconductor chip; a second semiconductor chip stacked on and electrically connected to the first semiconductor chip; a third semiconductor chip stacked on and electrically connected to the second semiconductor chip; a fourth semiconductor chip stacked on and electrically connected to the third semiconductor chip; and an encapsulant encapsulating the first semiconductor chip, the second semiconductor chip, the third semiconductor chip and the fourth semiconductor chip.
13. The package structure of claim 1, wherein the electronic device comprises: a first semiconductor chip; and an encapsulant encapsulating the first semiconductor chip, wherein the thermally conductive layer of the heat sink structure vertically overlaps the encapsulant of the electronic device.
15. The package structure of claim 13, wherein the electronic device further comprises: a second semiconductor chip stacked on and electrically connected to the first semiconductor chip; wherein the encapsulant further encapsulates the second semiconductor chip.
16. The package structure of claim 15, wherein a bottom surface of the second semiconductor chip contacts a top surface of the first semiconductor chip.
17. The package structure of claim 15, wherein the electronic device further comprises: a third semiconductor chip stacked on and electrically connected to the second semiconductor chip; wherein the encapsulant further encapsulates the third semiconductor chip.
18. The package structure of claim 17, wherein a bottom surface of the third semiconductor chip contacts a top surface of the second semiconductor chip.
19. The package structure of claim 17, wherein the electronic device further comprises: a fourth semiconductor chip stacked on and electrically connected to the third semiconductor chip; wherein the encapsulant further encapsulates the fourth semiconductor chip.
20. The package structure of claim 19, wherein a bottom surface of the fourth semiconductor chip contacts a top surface of the third semiconductor chip.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7, 9, 10, and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shih (U.S. Pub. 2022/0238487).
In re claim 1, Shih discloses a package structure, comprising an electronic device 100 (see paragraph [0081] and fig. 14); and a heat sink structure HDU disposed over the electronic device 100 (see paragraph [0050] and fig. 14), and comprising a thermally conductive layer (combination of 507,509,601) (see paragraphs [0077], [0079], [0086] and fig. 14); and a plurality of thermal vias 505 connecting to a second surface of the thermally conductive layer (507,509,601); wherein a first surface of the thermally conductive layer contacts a plurality of pads of the electronic device 100 as to dissipate a heat generated from the electronic device 100 to the thermal vias 505 (see paragraphs [0054], [0085], and fig. 14).
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In re claim 7, as applied to claim 1 above, Shih discloses wherein a lateral surface of the heat sink structure HDU is substantially aligned with a lateral surface of the electronic device 100 (see paragraphs [0050], [0081] and fig. 14).
In re claim 9, Shih discloses a manufacturing method, comprising providing an electronic device 100 (see paragraph [0081] and fig. 14); providing a heat sink structure HDU, wherein the heat sink structure includes a base portion 509, a plurality of thermal vias 505 disposed in the base portion 509 and a thermally conductive layer 507 embedded in the base portion 509 and connecting to the plurality of thermal vias 505 (see paragraphs [0054], [0077] and fig. 14); and thermally connecting the heat sink structure HDU to the electronic device 100, wherein the thermally conductive layer 507 is disposed between the plurality of thermal vias 505 and the electronic device 100 (see paragraphs [0050], [0054], [0077] and fig. 14).
In re claim 10, as applied to claim 9 above, Shih discloses wherein the thermally conductive layer (combination of 507,509,601) directly contacts the electronic device 100 (see paragraphs [0077], [0079], [0086] and fig. 14).
In re claim 12, as applied to claim 9 above, Shih discloses wherein the step of providing the heat sink structure includes providing the base portion 501; forming a recess portion in the base portion 501; forming a plurality of holes 503 in the recess portion; and forming the plurality of thermal vias 505 in the plurality of holes 503 and forming the thermally conductive layer 507 in the recess portion (see paragraphs [0051], [0054] and fig. 14).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (U.S. Pub. 2022/0238487) in view of Tong et al. (U.S. Pub. 2024/0379498).
In re claims 2 and 11, as applied to claims 1 and 9 above, respectively, Shih is silent to wherein the step of thermally connecting the heat sink structure to the electronic device is attaching the heat sink structure to the electronic device by hybrid bonding.
However, Tong discloses in a same field of endeavor, a package structure, including, inter-alia, wherein the step of thermally connecting the heat sink structure to the electronic device is attaching the heat sink structure 910 to the electronic device 240 by hybrid bonding (see paragraph [0109] and fig. 9B).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Tong into the manufacturing method of the electronic device of Shih in order to enable the process of wherein the step of thermally connecting the heat sink structure to the electronic device is attaching the heat sink structure to the electronic device by hybrid bonding in Shih to be performed in order to improve heat dissipation efficiency of the electronic device (see paragraph [0110] of Tong).
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (U.S. Pub. 2022/0238487) in view of Carbone et al. (U.S. Pub. 2011/0297361).
In re claims 3 and 4, as applied to claim 1 above, Shih is silent to wherein the thermally conductive layer has a net shape and wherein the thermally conductive layer includes a plurality of lines crossed with each other to form a plurality of intersection portions.
However, Carbone discloses in a same field of endeavor, a package structure, including, inter-alia, wherein the thermally conductive layer 1104 has a net shape (mesh shape) and wherein the thermally conductive layer includes a plurality of lines crossed with each other to form a plurality of intersection portions (see paragraph [0060] and 6A-11A).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Carbone into the package structure of Shih in order to enable wherein the thermally conductive layer has a net shape and wherein the thermally conductive layer includes a plurality of lines crossed with each other to form a plurality of intersection portions in Shih to be formed in order to obtain a low stress-inducing heat sink (see Abstract of Carbone).
In re claim 5, as applied to claim 4 above, Shih in combination with Carbone discloses wherein the plurality of thermal vias 1102 are connected to the plurality of intersection portions of the thermally conductive layer 1104 (see paragraph [0060] and figs. 6A-11A of Carbone).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (U.S. Pub. 2022/0238487) in view of Liu et al. (U.S. Pub. 2015/0044821).
In re claim 8, as applied to claim 1 above, Shih discloses wherein the electronic device comprises a first semiconductor chip 100; a second semiconductor chip 200 stacked on and electrically connected to the first semiconductor chip 100; a third semiconductor chip 300 stacked on and electrically connected to the second semiconductor chip 200; a fourth semiconductor chip 400 stacked on and electrically connected to the third semiconductor chip 300 (see paragraphs [0081], [0093], [0094], [0095] and fig. 14) but is silent to wherein an encapsulant encapsulating the first semiconductor chip, the second semiconductor chip, the third semiconductor chip and the fourth semiconductor chip.
However, Liu discloses in a same field of endeavor, a package structure, including, inter-alia, wherein an encapsulant 48 encapsulating the first semiconductor chip 41, the second semiconductor chip 42, the third semiconductor chip 43 and the fourth semiconductor chip 44 (see paragraph [0042] and fig. 4D).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Liu into the package structure of Shih in order to enable wherein an encapsulant encapsulating the first semiconductor chip, the second semiconductor chip, the third semiconductor chip and the fourth semiconductor chip in Shih to be formed in order to protect the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip from an outside environment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chandra (U.S. Pub. 2009/0024969) discloses a package structure, including, inter-alia, an electronic device 104-A; and a heat sink structure 150HSK disposed over the electronic device104-A, and comprising a thermally conductive layer; and a plurality of fins connecting to a second surface of the thermally conductive layer (see paragraph [0054] and fig. 2A).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
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