DETAILED ACTION
This action is responsive to the amended claims filed 7 Jul 2026. Claims 1-10 and 17-26 are pending, claims 3-5 are withdrawn from consideration, and claims 11-16 are cancelled. Claims 1, 17 and 21 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed 7 Jul 2026 has been entered. Claims 1-10 and 17-26 are currently pending in the application.
Title Objection
Applicant’s proposed title “Semiconductor Device having gate end dielectric structure” is still broad, but matches the existing claim language as required by 37 C.F.R. 1.72(a). If any further amendments are made, Applicant may be required to provide a more specific title that reflects the invention.
Election/Restrictions
Applicant’s election without traverse of product invention group I (claims 1-10 and 17-20), as well as Species Group I (Figures 5A-5I, asserted by applicant to involve claims 2, 6-10 and 17-20) in the reply filed on 2/13/2026 is acknowledged.
In the Specification, paragraph 50, the read bit line (RBL) is disclosed as being in the first metal layer (M1), the write word lines are disclosed as being in the second metal layer (M2) that is above M1, and the write bit line (WBL) and complementary write bit line (/WBL) are disclosed as being in the third metal layer (M3) that is above M2.
Claim 17 recites the RBL is in a “first metal layer” and the WBL & /WBL are in the “second metal layer” above the “first metal layer.” The terms “first” and “second” are ordinal terms that do not mean M1 and M2, but are understood to refer to M1 and M3, respectively; thus, the examiner agrees claims 17-20, as presented, read on the elected Species.
Applicant also added new claims 21-26 and asserts these new claims read on the elected invention and Species. For these claims, it is agreed they read on the elected Species, as indicated in Specification paragraph 50 (indicating the RBL is in M1, WWL is in M2, and WBL & /WBL are in M3).
Claims 3-5 are withdrawn from consideration as be directed to non-elected Species. Applicant may be entitled to rejoinder, should the antecedent claims be found allowable in a state the is generic to both the elected and non-elected species.
Examiner Note
The present application is very similar to Taiwan Semiconductor Manufacturing Company co-applications: 2024/0096383, 2023/0389260; 20230017584, 20250386481, 20250324561, and 20240304240. Each of the applications contain several of the same construction elements, but each claim 1 is sufficiently different (based on Read-Port gates, based on shared write-bit-line-bar, based on shared active areas, etc.) to preclude a non-statutory obvious double patenting rejection.
Response to Arguments
Applicant’s arguments filed on 7 Jul 2026 have been fully considered. While arguments have overcome the previous claim objections and 35 USC § 112 rejections, they are not persuasive in regards to the 35 USC § 103 rejections as the claims are currently written. Arguments and corresponding examiner’s responses are shown below for independent Claim 1. The same arguments are valid for the similar features of the other independent claims.
Argument 1: The applicant states (page 12) “Claim 18 stands objected to…”
Response 1: The applicant’s amendment has overcome the objection.
Argument 2: The applicant states (page 13) “In view of foregoing amendments in claim 18…”
Response 2: The examiner agrees and the 112(b) rejection has been overcome.
Argument 3: The applicant states (page 14) “independent claim 1 has been amended to recite a combination of elements including “a first gate end dielectric structure extending in the Y-direction…”
Response 3: The examiner respectfully disagrees. As repeated from the “Claim interpretation section of the first office action, the limitation of “a first gate-end dielectric structure” broadly comprises ANY structure that is (a) dielectric and (b) physically located between the two gate ends for independent claims 1, 17 and 21.
It appears that applicant wishes for examiner to import their more narrow structures from their specification paragraph 0063 of either a “shallow trench isolation structure”, or a “deep trench isolation structure” into the claims. Since neither of these structures are required by the claims, then the ONLY requirement is the existence of (a) a dielectric material, (b) physically residing between the two gate ends. Logically- a semiconductor component, such as that shown in Ishikura’s fig. 23-25 and figs. 36-38 comprises one of three things:
a type of dielectric semiconductor material,
a void, or
a type of metal.
In this office action, Ishikura’s description of “portions 93 and 94” from figure 23-25 have been added (completely in keeping the original thrust of the first rejection) to clearly show that Ishikura requires a dielectric semiconductor material - but neither a trench nor a void (see column 16, lines 27-47).
Likewise, Liaw-761’s figures 6A-6C with explanatory paragraphs 0063 requires a “gate-end dielectric features 640” which are also explicitly cited below, in keeping the original thrust that a dielectric material resides between all gate ends, not just the cited gate structures.
From the original office action: In the examinable claims, the following terms are employed: “gate end dielectric structure”; and “dielectric gate structure.”
The claimed invention relates to the layout of two adjacent 8T-SRAM cells that each have an L-shaped boundary for each cell, where “gate end dielectric structures” which is dielectric material between distinctly controllable gates (e.g., region 418-1 separating the first write pass gate WPG1 from the first read pass gate RPG) and separating cells in one column from cells in another (e.g., region 418-3 that is on the left-most side to separate the illustrated column from an unillustrated column that would be further to the left in the array).
The ”dielectric gate structures” are not gates, but simple dielectric material (e.g., 426-1) that aligns with the gate patterns for WPG1, RPG and WPG1’, serving as a fill-in dielectric.
The two Examiner’s Markups of Figure 5A, reproduced below, show the L-shaped SRAM on the left (i.e., the “first SRAM”) and the L-shaped SRAM on the right (i.e., the “second SRAM”) with their corresponding “gate end dielectric structures” and “dielectric gate structures.”
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However, these terms are not as narrow as illustrated in applicant’s Figures. Applicant has not specially defined the terms “gate end dielectric structure” or “dielectric gate structure.” They are accorded their broadest reasonable interpretation, consistent with the disclosure, as dielectric material that separates columns of cells from each other, as dielectric material that separates distinctly controllable gates from each other, or as dielectric material that fills gaps where a gate could have been but was not formed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-10, 21, 25, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Ishikura et al. (US 8665637) Figures in view of Liaw-761 (US 20200105761).
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Ishikura et al. show layout of at least two L-shaped 8T SRAM memory cells that have a write port and a single read port. The claimed transistors (i.e., WPGs, WPUs, WPDs, RPDs) are arranged as claimed, along with the required “rectangular” vias connected the WPD and RPD.
Some of the claims recite first and second “gate end dielectric structure[s]” that separate the read port from the write port of an SRAM, as well as third and fourth “gate end dielectric structure[s]” at the end boundary to separate columns of memory cells from each other.
Liaw-761 figures 6A-6C combined with paragraphs 0063 further teach ““a first gate end dielectric structure extending in the Y-direction and between a gate structure of the first WPD transistor and a gate structure of the first RPD transistor;”. In Liaw-761, this dielectric structure resides between all gate ends in the cited structure: “[0063] As shown in FIG. 6A, gate structures 630 are arranged substantially parallel to one another, and each has a length defined in an x-direction between the source/drain regions, and a width defined in a y-direction between gate end dielectric structures 640.
For this subject matter, Ishikura clearly teaches “portions 93 and 94” from figures 23-25 have been added (completely in keeping the original thrust of the first rejection) to clearly show that Ishikura requires a dielectric semiconductor material between the gates (see column 16, lines 27-47).
Therefore, as posited before, both Ishikura and Liaw-761 and Ishikura explicitly teach devices comprising of dielectric semiconductor material between the gate material.
As stated previously, these insulating layers that must be present to manufacture Ishikura’s 8T SRAM cell (Figs. 35, 36, 38) would necessarily be in the locations the “gate end dielectric structures” for further reason of preventing short circuits between independently controllable gate conductive lines for the read and write ports’ pass gate transistors (independently controlled by RWL and WWL respectively) and to prevent short circuits between adjacent columns of memory cells.
Some of claims additionally recite first and second “dielectric gate structures” that are dielectric material that separate what, without it, would have been one undesirable continuous conductive line. Again, although Ishikura et al. do not illustrate this detail, such insulating material is understood as required in order to manufacture Ishikura’s 8T SRAM illustrated in Figure 38. The closest illustration is Figure 36, showing the horizontal conductive gate control lines, and Figure 38 showing the gaps between these horizontal conductive gate control lines.
Furthermore, Liaw-761 explains that dielectric structures are utilized to generally isolate gate structures (see para. 24 and 0063). Liaw-761 even expressly mention the “gate end dielectric structure” that serve the same purpose of isolating gate structures, especially in adjacent columns. This purpose would serve to prevent undesirable short circuits on the circuitry designed to be independently controllable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have either understood the teachings of Ishikura et al. alone, or to combine the teachings of Liaw-761 to Ishikura et al., such that insulating structures (i.e., the claimed “gate end dielectric structure[s]” and “dielectric gate structures”) are utilized so Ishikura’s 8T SRAM can be manufactured as illustrated in Figure 38 with insulated regions to prevent short circuiting of the independently controllable features.
Claims 6’s and 10’s recitations to locations of the dielectric gate structures with respect to either the gate structures of the various transistors or the gate end dielectric structures (i.e., dielectric gate structures’ bottom surface below the gate end dielectric structures) is directed to a mere unpatentable rearrangement of parts because the locations would not result in any modification of operation of the device and would simply be obvious matter of design choice, per MPEP 2144.04(VI)(C).
Claims 2, 17-20, 22, 23 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Ishikura et al. (US 8665637) Figures in view of Liaw-761 (US 20200105761), as applied to independent claims 1 and 21 supra, in further view of Wang et al. (US 8294212).
For claims 2, 22, 23 and 24, Ishikura et al. explain their word lines are in a lower metal layer (Fig. 31: M3) and the write bit lines and read bit lines are in an upper metal layer (Fig. 34: M4) above the lower metal layer. These claims (together), however, require the read bit line to be in the metal layer (e.g., metal layer 1) lower than the word lines and the write bit lines to remain above the word lines.
Wang et al. teach moving only the read bit line to metal layer 1 (Fig. 8) as an improvement to 8T SRAM so as to permit the RBL to contact the read pass gate transistor only without intervening vias so as to improve access speed as explained in column 7, line 64 to column 8, line 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Wang et al. to the teachings of Ishikura et al. so as to rearrange the read bit line in a metal layer under the word lines’ metal layer for the reasons stated above.
For claims 17-20, Ishikura et al., alone or in combination with Liaw, teach the 8T-SRAM with structure (e.g., transistors, dielectric structures, arrangements) and the layout indicated above in the rejection of claims 1, 7-10, 21, 25 and 26.
Ishikura et al. explain their word lines are in a lower metal layer (Fig. 31: M3) and the write bit lines and read bit lines are in an upper metal layer (Fig. 34: M4) above the lower metal layer. These claims (together), however, require the read bit line to be in the metal layer (e.g., metal layer 1) lower than the write bit lines. Although the claim utilizes “first metal layer” and “second metal layer over the first metal layer,” the use of “first” and “second” are mere ordinal terms and do not actually mean metal layer M1 and metal layer M2.
Nevertheless, Wang et al. teach moving only the read bit line to metal layer 1 (Fig. 8) as an improvement to 8T SRAM so as to permit the RBL to contact the read pass gate transistor only without intervening vias so as to improve access speed as explained in column 7, line 64 to column 8, line 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Wang et al. to the teachings of Ishikura et al. so as to rearrange the read bit line in a metal layer under the word lines’ metal layer for the reasons stated above.
Claim 18 recites “a” source/drain contact to connect the source/drain “features” shared by the RPDs and WPDs to ground (as illustrated in Ishikura Fig. 33: via V2 for VSS or Fig.36’s contacts to VSS).
Claims 19 and 20 recite the locations of the source/drain contact (i.e., being “lower” or being lower by “a distance” or about 3nm to about 50nm) in relationship to the first and second gate end dielectric structures. As indicated above the source/drain contact is taught and the first and second gate end dielectric structures would have been obvious to employ in order to prevent short circuits. The location or distance is a mere unpatentable rearrangement of parts because the locations would not result in any modification of operation of the device and would simply be obvious matter of design choice, per MPEP 2144.04(VI)(C).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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