DETAILED ACTION
This action is responsive to the election and claims filed 13 Feb 2026 and the Information Disclosure Statement filed 12 Jun 2024. Claims 1-10 and 17-26 are pending, claims 3-5 are withdrawn from consideration, and claims 11-16 are cancelled. Claims 1, 17 and 21 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12 Jun 2024 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Title Objection
Applicant’s title is unacceptable because the title, “Semiconductor Device” is not specific as required by 37 C.F.R. 1.72(a). Applicant is required to provide a specific title that reflects the invention. Appropriate correction is required.
Election/Restrictions
Applicant’s election without traverse of product invention group I (claims 1-10 and 17-20), as well as Species Group I (Figures 5A-5I, asserted by applicant to involve claims 2, 6-10 and 17-20) in the reply filed on 2/13/2026 is acknowledged.
In the Specification, paragraph 50, the read bit line (RBL) is disclosed as being in the first metal layer (M1), the write word lines are disclosed as being in the second metal layer (M2) that is above M1, and the write bit line (WBL) and complementary write bit line (/WBL) are disclosed as being in the third metal layer (M3) that is above M2.
Claim 17 recites the RBL is in a “first metal layer” and the WBL & /WBL are in the “second metal layer” above the “first metal layer.” The terms “first” and “second” are ordinal terms that do not mean M1 and M2, but are understood to refer to M1 and M3, respectively; thus, the examiner agrees claims 17-20, as presented, read on the elected Species.
Applicant also added new claims 21-26 and asserts these new claims read on the elected invention and Species. For these claims, it is agreed they read on the elected Species, as indicated in Specification paragraph 50 (indicating the RBL is in M1, WWL is in M2, and WBL & /WBL are in M3).
Claims 3-5 are withdrawn from consideration as be directed to non-elected Species. Applicant may be entitled to rejoinder, should the antecedent claims be found allowable in a state the is generic to both the elected and non-elected species.
Examiner Note
The present application is very similar to Taiwan Semiconductor Manufacturing Company co-applications: 2024/0096383, 2023/0389260; 20230017584, 20250386481, 20250324561, and 20240304240. Each of the applications contain several of the same construction elements, but each claim 1 is sufficiently different (based on Read-Port gates, based on shared write-bit-line-bar, based on shared active areas, etc.) to preclude a non-statutory obvious double patenting rejection.
Claim Objections
Claim 18 is objected to because of the following informalities: clarity of “the WPD transistor.”
In claim 18, line 5, it appears applicant intended to indicate “a source/drain feature shared by the first WPD transistor and the second WPD transistor.”
Appropriate correction is required.
Claim Interpretation
In the examinable claims, the following terms are employed:
“gate end dielectric structure”; and
“dielectric gate structure.”
The claimed invention relates to the layout of two adjacent 8T-SRAM cells that each have an L-shaped boundary for each cell, where “gate end dielectric structures” which is dielectric material between distinctly controllable gates (e.g., region 418-1 separating the first write pass gate WPG1 from the first read pass gate RPG) and separating cells in one column from cells in another (e.g., region 418-3 that is on the left-most side to separate the illustrated column from an unillustrated column that would be further to the left in the array).
The ”dielectric gate structures” are not gates, but dielectric material (e.g., 426-1) that aligns with the gate patterns for WPG1, RPG and WPG1’, serving as a fill-in dielectric.
The two Examiner’s Markups of Figure 5A, reproduced below, show the L-shaped SRAM on the left (i.e., the “first SRAM”) and the L-shaped SRAM on the right (i.e., the “second SRAM”) with their corresponding “gate end dielectric structures” and “dielectric gate structures.”
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However, these terms are not as narrow as illustrated in applicant’s Figures. Applicant has not specially defined the terms “gate end dielectric structure” or “dielectric gate structure.” They are accorded their broadest reasonable interpretation, consistent with the disclosure, as dielectric material that separates columns of cells from each other, as dielectric material that separates distinctly controllable gates from each other, or as dielectric material that fills gaps where a gate could have been but was not formed.
Claim Rejections - 35 USC § 112(b) definiteness requirement
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Antecedent claim 18 requires the “source/drain contact” to be “over” “the first gate end dielectric structure and the second gate end dielectric structure.”
Claim 19, however, inconsistently recites the bottom surface of this “source/drain contact” is “lower than the top most surfaces of the first gate end dielectric structure and the second gate end dielectric structure.” The source/drain contact cannot be is formed within the first and second gate end dielectric structures (which is implied if the S/D contact’s bottom surface is lower than the top of the 1st and 2nd gate end dielectric structures), when the source/drain contact is over the first and second gate end dielectric structures.
Claim 20 also inconsistently recites a distance of 3nm to about 50nm from the bottom surface of the source/drain contact and the topmost surfaces of the first and second gate end dielectric structures. Again, this claim implies the source/drain contact is within the first and second gate dielectric structures by a depth of 3nm to 50nm, but if so, the source/drain contact would not be above the first and second gate end dielectric structures.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw, et al, U.S. Patent Application Publication 2022/0328499 (“Liaw”).
Regarding claim 1, Liaw teaches:
(Original) A semiconductor device, comprising: a first static random access memory (SRAM) cell, comprising: (Liaw, fig 3, “[0035] FIG. 3 shows a layout of the SRAM macro 102, particularly, a layout of certain layers ( or features) of the TP SRAM cells 104 according to another embodiment where the cells 104 include GAA transistors”; a double SRAM construction).
a first write port, comprising: a first write-port pass-gate (WPG) transistor, a second WPG transistor, a first write-port pull-down (WPD) transistor, and a second WPD transistor arranged in a Y-direction; and a first read port, comprising: a first read-port pull-down (RPD) transistor and a first read-port pass-gate (RPG) transistor; (Liaw, fig 3, 3.1, “[0036] Referring to FIG. 3-1, each cell 104 includes active regions 205 (including 205A, 205C, 205D, 205E, and 205F) that are oriented lengthwise along the “y” direction, and gate stacks 240 (including 240A, 240B, 240C, 240D, and 240E) that are oriented lengthwise along the “x” direction perpendicular to the “y” direction. … The gate stacks 240 engage the channel layers 215 of the respective active regions 205 to form the transistors R_PD, R_PG, W_PD-2, W_PG-2, W_PU-2, W_PU-1, W_PG-1, and W PD-1 in the same fashion as discussed with reference to FIG. 2-1, except that the transistors in FIG. 3-1 are GAA transistors.”; that a memory cell, 104-2, has all of the write pull-up, write pull-down, write pass gates, read pull down, and read pass gate are oriented lengthwise along the “y” direction, and vertically along the “x” direction).
a second SRAM cell, comprising: a second write port, comprising: a third WPG transistor, a fourth WPG transistor, a third WPD transistor, and a fourth WPD transistor arranged in the Y-direction; and a second read port, comprising: a second RPD transistor and a second RPG transistor, wherein the first RPD transistor, the first RPG transistor, the second RPD transistor, and the second RPG transistor are arranged in the Y-direction; (Liaw, fig 2, 3, 5, “[0027] Referring to FIG. 2, two TP SRAM cells 104, 104-1 and 104-2, are placed side-by-side and share a cell boundary line. They are referred to as “Cell-1” and “Cell-2,” respectively. [0039] FIGS. 4-1, 4-2, and 4-3 show different layers of a layout of 8 SRAM cells 104 arranged into a 2x4 array (2 rows and 4 columns). [0040] As shown in FIG. 4-1, at the M1 layer, the conductors are oriented lengthwise along the “y” direction. [0044] FIGS. 5-1 and 5-2 show the arrangement of cells 104 in a 2x4 array (two rows and four columns) according to an embodiment.”; twin cells 104-1 and 104-2 placed side-by-side, arranged in an array with identically constructed twin cells above, below, and side-to-side; that the cells are arranged in an “x” and “y” directions in a symmetrical mirror compared to memory cell 1, discussed in ppp 0036 above; for the purposes of this office action the first cell can be the top left cell of figures 4-1 or 5-1 and the second cell can be below the first cell because each of the cells has a similar layout).
a first gate end dielectric structure extending in the Y-direction and between the first write port and the first read port in an X-direction; and a second gate end dielectric structure extending in the Y-direction and between the second write port and the second read port in the X-direction. (Liaw, fig 2-3, “[0033] FIG. 2-3 shows the layout of the SRAM cells 104 at the M1 layer. … Referring to FIG. 2-3, the SRAM cells 104 further include various conductors at the M1 layer and each conductor is oriented lengthwise along the “y” direction. These conductors in Cell-1 include, from right to left, a read bit line (R_BL) conductor, a second Vss conductor, a second W WL landing pad, a write bit line bar (W BLB) conductor, a first V dd conductor, and a write bit line (W BL) conductor.”; that an M1 layer of memory cell 104-1 contains multiple “gate end” structures between the write port (the Write pass gate) and the read port (the read pass gate), that the symmetry of the gates in 104-2 has the same “second gate end” types of structures between the two pass gates; this is true of a “second cell” to the right of the “first cell” or below the “first cell”).
Regarding claim 2, Liaw teaches the semiconductor device of claim 1, further comprising: a first metal layer over the first SRAM cell and the second SRAM cell, (Liaw, fig 4-1, “[0040] FIG. 4-1 shows the layout at the M1 layer (the first metal layer above the via0 layer) and at the M2 layer (the second metal layer which is immediately above the first metal layer).”; a SRAM structure with 4x2 SRAMs attached).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-10, 21, 25, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Ishikura et al. (US 8665637) Figures in view of Liaw (US 20200105761).
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Ishikura et al. show layout of at least two L-shaped 8T SRAM memory cells that have a write port and a single read port. The claimed transistors (i.e., WPGs, WPUs, WPDs, RPDs) are arranged as claimed, along with the required “rectangular” vias connected the WPD and RPD.
Some of the claims recite first and second “gate end dielectric structure[s]” that separate the read port from the write port of an SRAM, as well as third and fourth “gate end dielectric structure[s]” at the end boundary to separate columns of memory cells from each other.
For this subject matter, although Ishikura et al. does not show the side views of the SRAM cells, interlayer insulating (i.e., dielectric) layers would have been understood as required in order to manufacture the various layers on top of each, as is illustrated because for not only the reason that the materials cannot be formed on open space. These insulating layers that must be present to manufacture Ishikura’s 8T SRAM cell (Figs. 35, 36, 38) would necessarily be in the locations the “gate end dielectric structures” for further reason of preventing short circuits between independently controllable gate conductive lines for the read and write ports’ pass gate transistors (independently controlled by RWL and WWL respectively) and to prevent short circuits between adjacent columns of memory cells.
Some of claims additionally recite first and second “dielectric gate structures” that are dielectric material that separate what, without it, would have been one undesirable continuous conductive line. Again, although Ishikura et al. do not illustrate this detail, such insulating material is understood as required in order to manufacture Ishikura’s 8T SRAM illustrated in Figure 38. The closest illustration is Figure 36, showing the horizontal conductive gate control lines, and Figure 38 showing the gaps between these horizontal conductive gate control lines.
Furthermore, Liaw explains that dielectric structures are utilized to generally isolate gate structures (see para. 24). Liaw even expressly mention the “gate end dielectric structure” that serve the same purpose of isolating gate structures, especially in adjacent columns. This purpose would serve to prevent undesirable short circuits on the circuitry designed to be independently controllable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have either understood the teachings of Ishikura et al. alone, or to combine the teachings of Liaw to Ishikura et al., such that insulating structures (i.e., the claimed “gate end dielectric structure[s]” and “dielectric gate structures”) are utilized so Ishikura’s 8T SRAM can be manufactured as illustrated in Figure 38 with insulated regions to prevent short circuiting of the independently controllable features.
Claims 6’s and 10’s recitations to locations of the dielectric gate structures with respect to either the gate structures of the various transistors or the gate end dielectric structures (i.e., dielectric gate structures’ bottom surface below the gate end dielectric structures) is directed to a mere unpatentable rearrangement of parts because the locations would not result in any modification of operation of the device and would simply be obvious matter of design choice, per MPEP 2144.04(VI)(C).
Claims 2, 17-20, 23 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Ishikura et al. (US 8665637) Figures in view of Liaw (US 20200105761), as applied to independent claims 1 and 21 supra, in further view of Wang et al. (US 8294212).
For claims 2, 23 and 24, Ishikura et al. explain their word lines are in a lower metal layer (Fig. 31: M3) and the write bit lines and read bit lines are in an upper metal layer (Fig. 34: M4) above the lower metal layer. These claims (together), however, require the read bit line to be in the metal layer (e.g., metal layer 1) lower than the word lines and the write bit lines to remain above the word lines.
Wang et al. teach moving only the read bit line to metal layer 1 (Fig. 8) as an improvement to 8T SRAM so as to permit the RBL to contact the read pass gate transistor only without intervening vias so as to improve access speed as explained in column 7, line 64 to column 8, line 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Wang et al. to the teachings of Ishikura et al. so as to rearrange the read bit line in a metal layer under the word lines’ metal layer for the reasons stated above.
For claims 17-20, Ishikura et al., alone or in combination with Liaw, teach the 8T-SRAM with structure (e.g., transistors, dielectric structures, arrangements) and the layout indicated above in the rejection of claims 1, 7-10, 21, 25 and 26.
Ishikura et al. explain their word lines are in a lower metal layer (Fig. 31: M3) and the write bit lines and read bit lines are in an upper metal layer (Fig. 34: M4) above the lower metal layer. These claims (together), however, require the read bit line to be in the metal layer (e.g., metal layer 1) lower than the write bit lines. Although the claim utilizes “first metal layer” and “second metal layer over the first metal layer,” the use of “first” and “second” are mere ordinal terms and do not actually mean metal layer M1 and metal layer M2.
Nevertheless, Wang et al. teach moving only the read bit line to metal layer 1 (Fig. 8) as an improvement to 8T SRAM so as to permit the RBL to contact the read pass gate transistor only without intervening vias so as to improve access speed as explained in column 7, line 64 to column 8, line 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Wang et al. to the teachings of Ishikura et al. so as to rearrange the read bit line in a metal layer under the word lines’ metal layer for the reasons stated above.
Claim 18 recites “a” source/drain contact to connect the source/drain “features” shared by the RPDs and WPDs to ground (as illustrated in Ishikura Fig. 33: via V2 for VSS or Fig.36’s contacts to VSS).
Claims 19 and 20 recite the locations of the source/drain contact (i.e., being “lower” or being lower by “a distance” or about 3nm to about 50nm) in relationship to the first and second gate end dielectric structures. As indicated above the source/drain contact is taught and the first and second gate end dielectric structures would have been obvious to employ in order to prevent short circuits. The location or distance is a mere unpatentable rearrangement of parts because the locations would not result in any modification of operation of the device and would simply be obvious matter of design choice, per MPEP 2144.04(VI)(C).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
Prosecution Insights