Prosecution Insights
Last updated: October 01, 2026
Application No. 18/741,654

DEVICES WITH THROUGH SILICON VIAS, GUARD RINGS AND METHODS OF MAKING THE SAME

Non-Final OA §103
Filed
Jun 12, 2024
Priority
Feb 10, 2021 — provisional 63/148,079 +1 more
Examiner
VU, VU A
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1258 granted / 1362 resolved
+32.4% vs TC avg
Moderate +7% lift
Without
With
+6.6%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
44 currently pending
Career history
1381
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
46.5%
+6.5% vs TC avg
§102
31.3%
-8.7% vs TC avg
§112
15.0%
-25.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1362 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Filippi et al. (U.S. Patent No. 9,082,781) in view of Teng et al. (U.S. Patent No. 10,515,908). Regarding to claim 1, Filippi teaches a semiconductor structure, comprising: a semiconductor substrate (Fig. 5E, element 112, column 3, lines 55-56); a wiring structure over the semiconductor substrate (Fig. 5E, element 114A/B/C), the wiring structure including a plurality of conductive layers (Fig. 5E, element 140, column 4, lines 50-51) and an insulating material (Fig. 5E, element 142, column 4, lines 50-51); a through via within the semiconductor substrate and the wiring structure (Fig. 5E, element 122, column 5, lines 8-9); and a guard ring within the wiring structure and laterally surrounding the through via, wherein the guard ring includes a plurality of guard ring elements (Fig. 5E, elements 144, column 5, lines 12-14), each of the plurality of guard ring elements has varied widths (Fig. 5E, each ring has the top portion larger than the bottom portion). Filippi does not explicitly disclose thicknesses of the plurality of guard ring elements decrease from a top side of the wiring structure towards the semiconductor substrate. Teng discloses thicknesses of the plurality of ring elements decrease from a top side of the wiring structure towards the semiconductor substrate (Fig. 7, column 8, lines 41-44). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Filippi in view of Teng to decrease thicknesses of the plurality of guard ring elements from a top side of the wiring structure towards the semiconductor substrate in order to balance impedances through the stack. Regarding to claim 2, Filippi teaches one or more of the plurality of guard ring elements are in electrical communication with electrically conductive features of the wiring structure (Fig. 5E, the guard ring elements are formed close to the electrically conductive features of the wiring structure, thus inductive reaction occurs). Regarding to claim 3, Filippi teaches one or more of the plurality of guard ring elements comprise an electrically conductive material (the guard rings are made from same material with the wires, which are metal). Regarding to claim 4, Filippi teaches each of the plurality of guard ring elements is adjacent to another one of the plurality of guard ring elements (Fig. 5E). Regarding to claim 15, Filippi teaches a semiconductor structure, comprising: a semiconductor substrate (Fig. 5E, element 112, column 3, lines 55-56); a wiring structure over the semiconductor substrate (Fig. 5E, element 114A/B/C), the wiring structure including a plurality of conductive layers (Fig. 5E, element 140, column 4, lines 50-51) and an insulating material (Fig. 5E, element 142, column 4, lines 50-51); a through via within the semiconductor substrate and the wiring structure (Fig. 5E, element 122, column 5, lines 8-9); and a guard ring within the wiring structure and laterally surrounding the through via, wherein the guard ring includes a plurality of guard ring elements (Fig. 5E, elements 144, column 5, lines 12-14), each of the plurality of guard ring elements includes: an upper section having a first thickness (Fig. 5E, upper portion of ring 144 in each layer 114), and a lower section of having a second thickness (Fig. 5E, lower portion of ring 144 in each layer 114). Filippi does not explicitly disclose a ratio of the first thickness to the second thickness decreases from a top side of the wiring structure towards the semiconductor substrate. Teng discloses a ratio of the first thickness to the second thickness decreases from a top side of the wiring structure towards the semiconductor substrate (Fig. 7, column 8, lines 41-44). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Filippi in view of Teng to decrease a ratio of the first thickness to the second thickness decreases from a top side of the wiring structure towards the semiconductor substrate in order to balance impedances through the stack. Regarding to claim 16, Filippi teaches inner surfaces of three or more of the plurality of guard ring elements are coplanar with each other (Fig.5E). Regarding to claim 17, Filippi teaches one or more of the plurality of guard ring elements are in electrical communication with electrically conductive features of the wiring structure (Fig. 5E, the guard ring elements are formed close to the electrically conductive features of the wiring structure, thus inductive reaction occurs). Regarding to claim 18, Filippi teaches one or more of the plurality of guard ring elements comprise an electrically conductive material (the guard rings are made from same material with the wires, which are metal). Regarding to claim 19, Filippi teaches each of the plurality of guard ring elements is adjacent to another one of the plurality of guard ring elements (Fig. 5E). Claims 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Filippi et al. (U.S. Patent No. 9,082,781) in view of Kawano et al. (U.S. Patent No. 7,633,167). Regarding to claim 7, Filippi teaches a semiconductor structure, comprising: a semiconductor substrate (Fig. 5E, element 112, column 3, lines 55-56); a wiring structure over the semiconductor substrate (Fig. 5E, element 114A/B/C), the wiring structure including a plurality of conductive layers (Fig. 5E, element 140, column 4, lines 50-51) and an insulating material (Fig. 5E, element 142, column 4, lines 50-51); a through via within the semiconductor substrate and the wiring structure (Fig. 5E, element 122, column 5, lines 8-9); and a guard ring within the wiring structure and laterally surrounding the through via, wherein the guard ring includes an inner surface facing the through via (Fig. 5E, elements 144, column 5, lines 12-14), each of the plurality of guard ring elements has varied widths (Fig. 5E, each ring has the top portion larger than the bottom portion). Filippi does not explicitly disclose a distance between the inner surface and the through via increases from a top side of the wiring structure towards the semiconductor substrate. Kawano discloses a ring includes an inner surface facing the through via, and a distance between the inner surface and the through via increases from a top side of the wiring structure towards the semiconductor substrate (Fig. 28, Cu/W ring includes an inner surface facing the through via, and a distance between the inner surface and the through via increases from a top side of the wiring structure towards the semiconductor substrate). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Filippi in view of Kawano to increase distance between the inner surface and the through via from a top side of the wiring structure towards the semiconductor substrate in order to increase etching process tolerance. Regarding to claim 8, Kawano discloses the distance between the inner surface and the through via increases linearly from the top side of the wiring structure towards the semiconductor structure (Fig. 28). Regarding to claim 9, Kawano discloses the inner surface of the guard ring is cylindrical in shape (Fig. 20). Regarding to claim 10, Filippi teaches one or more of the plurality of guard ring elements are in electrical communication with electrically conductive features of the wiring structure (Fig. 5E, the guard ring elements are formed close to the electrically conductive features of the wiring structure, thus inductive reaction occurs). Regarding to claim 11, Filippi teaches one or more of the plurality of guard ring elements comprise an electrically conductive material (the guard rings are made from same material with the wires, which are metal). Regarding to claim 12, Filippi teaches each of the plurality of guard ring elements is adjacent to another one of the plurality of guard ring elements (Fig. 5E). Claims 1-7 and 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Farooq et al. (U.S. Patent No. 9,536,829). Regarding to claim 1, Farooq teaches a semiconductor structure, comprising: a semiconductor substrate (Fig. 14, element 102, column 5, line 12); a wiring structure over the semiconductor substrate (Fig. 14, element 302/312/314, column 10, lines 38-40), the wiring structure including a plurality of conductive layers (Fig. 14, element 304/310, column 10, lines 23-25) and an insulating material (Fig. 14, element 306, column 10, lines 22-24); a through via within the semiconductor substrate and the wiring structure (Fig. 14, element 120, column 10, lines 53-54); and a guard ring within the wiring structure and laterally surrounding the through via, wherein the guard ring includes a plurality of guard ring elements (Fig. 14, element 308, column 10, lines 41-42), each of the plurality of guard ring elements has varied widths (Fig. 14, each ring has the top portion larger than the bottom portion). Farooq does not explicitly disclose thicknesses of the plurality of guard ring elements decrease from a top side of the wiring structure towards the semiconductor substrate. However, it would have been an obvious matter of design choice to configure thicknesses of the plurality of guard ring elements decreasing from a top side of the wiring structure towards the semiconductor substrate, since applicant has not disclosed that the difference in thickness solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well without the difference. Regarding to claim 2, Farooq teaches one or more of the plurality of guard ring elements are in electrical communication with electrically conductive features of the wiring structure (Fig. 14, element 118). Regarding to claim 3, Farooq teaches one or more of the plurality of guard ring elements comprise an electrically conductive material (column 5, lines 31-33, the guard rings are made from same material with the wires, which are metal). Regarding to claim 4, Farooq teaches each of the plurality of guard ring elements is adjacent to another one of the plurality of guard ring elements (Fig. 14). Regarding to claim 5, Farooq teaches one or more of the plurality of guard ring elements comprise Copper (column 5, lines 42-43). Regarding to claim 6, Farooq teaches one or more of the plurality of guard ring elements comprise Aluminum (column 5, lines 42-43). Regarding to claim 7, Farooq teaches a semiconductor structure, comprising: a semiconductor substrate (Fig. 14, element 102, column 5, line 12); a wiring structure over the semiconductor substrate (Fig. 14, element 302/312/314, column 10, lines 38-40), the wiring structure including a plurality of conductive layers (Fig. 14, element 304/310, column 10, lines 23-25) and an insulating material (Fig. 14, element 306, column 10, lines 22-24); a through via within the semiconductor substrate and the wiring structure (Fig. 14, element 120, column 10, lines 53-54); and a guard ring within the wiring structure and laterally surrounding the through via, wherein the guard ring includes an inner surface facing the through via (Fig. 14, element 308, column 10, lines 41-42). Farooq does not explicitly disclose a distance between the inner surface and the through via increases from a top side of the wiring structure towards the semiconductor substrate. However, it would have been an obvious matter of design choice to configure a distance between the inner surface and the through via increasing from a top side of the wiring structure towards the semiconductor substrate, since applicant has not disclosed that the difference in distance solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well without the difference. Regarding to claim 9, Farooq teaches the inner surface of the guard ring is cylindrical in shape (Fig. 4). Regarding to claim 10, Farooq teaches one or more of the plurality of guard ring elements are in electrical communication with electrically conductive features of the wiring structure (Fig. 14, element 118). Regarding to claim 11, Farooq teaches one or more of the plurality of guard ring elements comprise an electrically conductive material (column 5, lines 31-33, the guard rings are made from same material with the wires, which are metal). Regarding to claim 12, Farooq teaches each of the plurality of guard ring elements is adjacent to another one of the plurality of guard ring elements (Fig. 14). Regarding to claim 13, Farooq teaches one or more of the plurality of guard ring elements comprise Copper (column 5, lines 42-43). Regarding to claim 14, Farooq teaches one or more of the plurality of guard ring elements comprise Aluminum (column 5, lines 42-43). Regarding to claim 15, Farooq teaches a semiconductor structure, comprising: a semiconductor substrate (Fig. 14, element 102, column 5, line 12); a wiring structure over the semiconductor substrate (Fig. 14, element 302/312/314, column 10, lines 38-40), the wiring structure including a plurality of conductive layers (Fig. 14, element 304/310, column 10, lines 23-25) and an insulating material (Fig. 14, element 306, column 10, lines 22-24); a through via within the semiconductor substrate and the wiring structure (Fig. 14, element 120, column 10, lines 53-54); and a guard ring within the wiring structure and laterally surrounding the through via (Fig. 14, element 308, column 10, lines 41-42), wherein the guard ring includes a plurality of guard ring elements, each of the plurality of guard ring elements includes: an upper section having a first thickness (Fig. 14, upper portion of ring 308 in each layer 302/312/314), and a lower section of having a second thickness (Fig. 14, lower portion of ring 308 in each layer 302/312/314). Farooq does not explicitly disclose a ratio of the first thickness to the second thickness decreases from a top side of the wiring structure towards the semiconductor substrate. However, it would have been an obvious matter of design choice to configure a ratio of the first thickness to the second thickness decreasing from a top side of the wiring structure towards the semiconductor substrate, since applicant has not disclosed that the difference in thickness solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well without the difference. Regarding to claim 16, Farooq teaches inner surfaces of three or more of the plurality of guard ring elements are coplanar with each other (Fig. 14). Regarding to claim 17, Farooq teaches one or more of the plurality of guard ring elements are in electrical communication with electrically conductive features of the wiring structure (Fig. 14, element 118). Regarding to claim 18, Farooq teaches one or more of the plurality of guard ring elements comprise an electrically conductive material (column 5, lines 31-33, the guard rings are made from same material with the wires, which are metal). Regarding to claim 19, Farooq teaches each of the plurality of guard ring elements is adjacent to another one of the plurality of guard ring elements (Fig. 14). Regarding to claim 20, Farooq teaches one or more of the plurality of guard ring elements comprise Copper or Aluminum (column 5, lines 42-43). Pertinent Art For the benefits of the Applicant, US-20150348874-A1, US-11127654-B2, US-10734430-B2, US-11508619-B2, US-8890293-B2, and US-8232648-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to disclose “the guard ring includes a plurality of guard ring elements, each of the plurality of guard ring elements has varied widths, and thicknesses of the plurality of guard ring elements decrease from a top side of the wiring structure towards the semiconductor substrate.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VU A VU/Primary Examiner, Art Unit 2897
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Prosecution Timeline

Jun 12, 2024
Application Filed
Aug 27, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+6.6%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1362 resolved cases by this examiner. Grant probability derived from career allowance rate.

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