DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/13/2024 was filed before the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by (US Pat. 9,837,357).
Re claim 1, Adusumilli teaches a method (Figs. 9-12), comprising: forming, on a substrate (902), a first doped semiconductor region (905) with a first type conductivity (N); forming, on the substrate (902), a second doped semiconductor region (911) with a second type conductivity (P); forming a first silicide layer (1002) on the first doped semiconductor region (905); forming a second silicide layer (1102) on the first silicide layer (1002); forming a doped silicide layer (1102) on the second doped semiconductor region (911); and depositing first (1202, “device 910”) and second (1202, “device 912”) conductive layers on the second silicide layer (1102, “device 910”) and the doped silicide layer (1102, “device 912”), respectively.
Prior art of record
Re claim 11, Adusumilli (US Pat. 9,837,357) teaches a method (Figs. 9-12), comprising: forming a source/drain region (905) on a substrate (902); and forming, on the source/drain region (905), a conductive structure (1002). Adusumilli does not explicitly teach depositing a first metal layer on the source/drain region; converting the first metal layer to a doped silicide layer on the source/drain region; and depositing a second metal layer on the doped silicide layer.
Re claim 17, Adusumilli (US Pat. 9,837,357) teaches a semiconductor device, comprising: a substrate (902); a fin structure (906) disposed on the substrate (902); a source/drain region (905) disposed on the fin structure (906); and a contact structure (918), comprising: a zirconium-based layer disposed on the source/drain region (Co. 8, lines 64-67 and Col. 9, lines 1-25). Adusumilli does not explicitly teach a transition metal doped silicide layer disposed on zirconium-based layer; a dipole layer disposed at an interface between the zirconium-based layer and the source/drain region; and a metal layer disposed on the transition metal doped silicide layer.
Allowable Subject Matter
Claims 2-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Re claim 2, Adusumilli teaches the method of claim 1, yet remains explicitly silent to wherein forming the first silicide layer comprises depositing a metal layer on the first doped semiconductor region without depositing the metal layer on the second doped semiconductor region.
Re claim 3, Adusumilli teaches the method of claim 1, yet remains explicitly silent to wherein forming the second silicide layer comprises: depositing a dopant source layer on the first silicide layer; and depositing a metal layer on the dopant source layer. Re claim 4, Adusumilli teaches the method of claim 1, yet remains explicitly silent to wherein forming the second silicide layer comprises forming a transition metal doped silicide layer. Re claim 5, Adusumilli teaches the method of claim 1, yet remains explicitly silent to wherein forming the second silicide layer comprises forming an undoped silicide layer. Re claim 6, Adusumilli teaches the method of claim 1, yet remains explicitly silent to wherein forming the doped silicide layer comprises: depositing a transition metal layer on the second doped semiconductor region; and depositing a metal layer on the transition metal layer.
Re claim 7, Adusumilli teaches the method of claim 1, yet remains explicitly silent to wherein forming the doped silicide layer comprises: depositing, on the second doped semiconductor region, a first metal layer with a first electronegativity value; and depositing, on the first metal layer, a second metal layer with a second electronegativity value greater than the first electronegativity value.
Re claim 8, Adusumilli teaches the method of claim 1, yet remains explicitly silent to wherein forming the doped silicide layer comprises forming a transition metal doped silicide layer with a dopant concentration profile having a peak dopant concentration at an interface between the transition metal doped silicide layer and the second doped semiconductor region.
Re claim 9, Adusumilli teaches the method of claim 1, yet remains explicitly silent to further comprising performing an anneal process on the doped silicide layer prior to depositing the second conductive layer.
Re claim 10, Adusumilli teaches the method of claim 1, yet remains explicitly silent to further comprising forming a zirconium-based ternary compound layer between the doped silicide layer and the second doped semiconductor region.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not anticipate or make obvious the method of claim 11, including each of the limitations and specifically depositing a first metal layer on the source/drain region; converting the first metal layer to a doped silicide layer on the source/drain region; and depositing a second metal layer on the doped silicide layer, for the same reasons as mentioned for claim 11 in the prior art of record above.
The prior art of record does not anticipate or make obvious the device of claim 17, including each of the limitations and specifically a transition metal doped silicide layer disposed on zirconium-based layer; a dipole layer disposed at an interface between the zirconium-based layer and the source/drain region; and a metal layer disposed on the transition metal doped silicide layer, for the same reasons as mentioned for claim 17 in the prior art of record above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached on M-F 9-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
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