DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
The term “about” in claims 12-14 is a relative term which renders the claim indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. This term will not be read into the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Van der Straten (U.S. PGPub 2025/0300066) in view of Chikaki (U.S. PGPub 2012/0025395).
Regarding claim 1, Van der Straten teaches a semiconductor device (Figs. 10-11, [0066]), comprising:
a substrate ([0030]),
a bottom interconnector layer positioned in the substrate (M1/V1 line/via, [0030]),
a bottom dielectric layer positioned on the substrate (106/206, [0033], [0067]),
an interconnector structure positioned along the bottom dielectric layer, positioned on the bottom interconnector layer, and positioned on the bottom dielectric layer (120/220, [0067]-[0068], [0073]),
a plurality of liners laterally positioned between the bottom dielectric layer and the interconnector structure and vertically positioned between the interconnector structure and the bottom interconnector layer (116/216, [0067], [0041], multiple layers),
a top glue layer conformally positioned on the bottom dielectric layer and the interconnector structure (128/228, [0067], [0053]), and
a top dielectric layer positioned surrounding the top glue layer (132/232, [0055], [0067]),
wherein a top surface of the top glue layer and a top surface of the top dielectric layer are substantially coplanar (Fig. 11, [0068]).
Van der Straten teaches wherein the top dielectric comprises a low-k material ([0031], [0057]) but does not explicitly teach wherein the top dielectric layer is porous.
Chikaki teaches a semiconductor device comprising a substrate and a bottom interconnector layer in the substrate (1, 3, [0036]), a bottom dielectric layer positioned on the substrate (6, [0036]), an interconnector positioned along the bottom dielectric layer, positioned on the bottom interconnector layer, and positioned on the bottom dielectric layer (11, [0036]), a top dielectric layer positioned on the bottom dielectric layer and surrounding the interconnector structure (7, [0036]), wherein the top dielectric layer is porous ([0037]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Chikaki with Van der Straten such that the top dielectric layer is porous for the purpose of providing a low-k dielectric layer with high mechanical strength and adhesion (Chikaki, [0042]).
Regarding claim 2, the combination of Van der Straten and Chikaki teaches wherein the bottom dielectric layer is porous (Chikaki, [0042]; Van der Straten, [0033]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Van der Straten and Chikaki for the reasons set forth in the rejection of claim 1.
Regarding claim 3, the combination of Van der Straten and Chikaki teaches wherein a porosity of the top dielectric layer is greater than a porosity of the bottom dielectric layer (Chikaki, [0043]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Van der Straten and Chikaki for the reasons set forth in the rejection of claim 1.
Regarding claim 4, the combination of Van der Straten and Chikaki does not explicitly teach wherein the porosity of the bottom dielectric layer is greater than a porosity of the top glue layer.
The combination of Van der Straten and Chikaki teaches wherein the bottom dielectric layer is a low-k layer which is porous to reduce the dielectric constant (Van der Straten, [0033], [0031]; Chikaki, [0005], [0016]), and wherein the top glue layer is not a low-k layer (Van der Straten, [0053], SiNx, SiNC).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Van der Straten and Chikaki such that the porosity of the bottom dielectric layer is greater than a porosity of the top glue layer for the purpose of forming the bottom dielectric layer as a low-k layer and the top glue layer as not a low-k layer.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Van der Straten (U.S. PGPub 2025/0300066) in view of Chikaki (U.S. PGPub 2012/0025395) and Lee (U.S. PGPub 2019/0244896).
Regarding claim 5, the combination of Van der Straten and Chikaki does not explicitly teach a bottom glue layer positioned between the substrate and the bottom dielectric layer, wherein the bottom glue layer and the top glue layer comprise the same material.
Lee teaches a bottom interconnector positioned in a substrate (35/22/21, [0012]-[0014]), an interconnector structure positioned in and along a bottom dielectric layer (71, 46, [0012]-[0014]), and a bottom glue layer positioned between the substrate and the bottom dielectric layer (45, [0015], [0038]), wherein the glue layer may be a lower porosity layer which is SiN or SiCN ([0038]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Lee with Van der Straten and Chikaki such that the device comprises a bottom glue layer positioned between the substrate and the bottom dielectric layer, wherein the bottom glue layer and the top glue layer comprise the same material for the purpose of providing a glue layer (Lee, [0037]-[0038]).
Regarding claim 6, the combination of Van der Straten, Chikaki, and Lee teaches wherein the interconnector structure comprises a conductive layer comprising a vertical segment positioned along the bottom dielectric layer and the bottom glue layer, and positioned on the bottom interconnector layer and a horizontal segment positioned on the vertical segment and on the bottom dielectric layer, wherein the plurality of liners are laterally positioned between the vertical segment and the bottom dielectric layer and vertically positioned between the horizontal segment and the bottom interconnector layer (Van der Straten, 220, Fig. 11). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Van der Straten, Chikaki, and Lee for the reasons set forth in the rejection of claim 5.
Regarding claim 7, the combination of Van der Straten, Chikaki, and Lee teaches wherein a width of the horizontal segment is greater than a width of the vertical segment (Van der Straten, 220, Fig. 11). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Van der Straten, Chikaki, and Lee for the reasons set forth in the rejection of claim 5.
Claims 8-11 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Van der Straten (U.S. PGPub 2025/0300066) in view of Chikaki (U.S. PGPub 2012/0025395), Lee (U.S. PGPub 2019/0244896), and Wang (U.S. Pat. 6465343).
Regarding claim 8, the combination of Van der Straten, Chikaki, and Lee does not explicitly teach a hard mask layer positioned on the horizontal segment, wherein the top glue layer conformally covers the hard mask layer.
Wang teaches a hard mask layer positioned on the top surface of an interconnector structure, wherein a SiN or SiC liner conformally covers the hard mask layer (Fig. 11, 34, 38, 46, col. 4, l. 39-58; col. 5, l. 20-25).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Wang with Van der Straten, Chikaki, and Lee such that the device comprises a hard mask layer positioned on the horizontal segment, wherein the top glue layer conformally covers the hard mask layer for the purpose of using the hard mask to etch the interconnector structure (Wang, col. 4, l. 39-68).
Regarding claim 9, the combination of Van der Straten, Chikaki, Lee, and Wang teaches wherein a width of the hard mask layer and the width of the horizontal segment are substantially the same (Wang, Fig. 11). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Van der Straten, Chikaki, Lee, and Wang for the reasons set forth in the rejection of claim 8.
Regarding claim 10, the combination of Van der Straten, Chikaki, Lee, and Wang teaches a barrier layer positioned between the horizontal segment and the bottom dielectric layer, between the plurality of liners and the bottom dielectric layer, and between the vertical segment and the bottom interconnector layer (Van der Straten, [0041]; Lee, [0052]-[0054]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Van der Straten, Chikaki, Lee, and Wang for the purpose of providing suitable barrier and liner layers for an interconnector structure according to Van der Straten and Lee.
Regarding claim 11, the combination of Van der Straten, Chikaki, Lee, and Wang teaches wherein the conductive layer comprises a nucleation portion positioned between the horizontal segment and the barrier layer, between the vertical segment and the plurality of liners, and between the vertical segment and the barrier layer (Van der Straten, [0040]-[0041]; Lee, 66, [0052]-[0054]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Van der Straten, Chikaki, Lee, and Wang for the purpose of providing a suitable nucleation portion for an interconnector structure according to Van der Straten and Lee.
Regarding claim 13, the combination of Van der Straten, Chikaki, Lee, and Wang teaches wherein the porosity of the top dielectric layer is greater than 50% (Chikaki, [0037], 40% plus 10% or more). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Van der Straten, Chikaki, Lee, and Wang for the reasons set forth in the rejections of claims 8 and 10.
Regarding claim 14, the combination of Van der Straten, Chikaki, Lee, and Wang teaches wherein the porosity of the bottom dielectric layer is 40% or below (Chikaki, [0037]). In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists. See MPEP 2144.05. Therefore it would have been obvious to a person having ordinary skill in the art to further combine the teachings of Van der Straten, Chikaki, Lee, and Wang such that wherein the porosity of the bottom dielectric layer is between 20% and 50%.
Regarding claim 15, the combination of Van der Straten, Chikaki, Lee, and Wang teaches wherein the conductive layer comprises tungsten, copper, aluminum, or a combination thereof (Van der Straten, [0045]; Chikaki, [0039]; Lee, [0053]; Wang, col. 4, l. 40-45). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Van der Straten, Chikaki, Lee, and Wang for the reasons set forth in the rejections of claims 8 and 10.
Regarding claim 16, the combination of Van der Straten, Chikaki, Lee, and Wang teaches wherein the plurality of liners comprise titanium, titanium nitride, titanium-tungsten alloy, tantalum, tantalum nitride, or the combination thereof (Van der Straten, [0041]; Chikaki, [0039]; Lee, [0053]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Van der Straten, Chikaki, Lee, and Wang for the reasons set forth in the rejections of claims 8 and 10.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Van der Straten (U.S. PGPub 2025/0300066) in view of Chikaki (U.S. PGPub 2012/0025395), Lee (U.S. PGPub 2019/0244896), Wang (U.S. Pat. 6465343), and Kim (U.S. PGPub 2023/0231027).
Regarding claim 12, the combination of Van der Straten, Chikaki, Lee, and Wang does not explicitly teach wherein the porosity of the top glue layer is less than 5%.
Lee teaches wherein a glue layer has lower porosity than the adjacent interlayer dielectric ([0038]).
Kim teaches wherein a dielectric liner adjacent to a metal element has a porosity of less than 5% ([0053]-[0055]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kim with Van der Straten, Chikaki, Lee, and Wang such that the porosity of the top glue layer is less than 5% for the purpose of providing a glue layer with a low porosity that prevents metal diffusion (Lee, [0038]; Kim, [0055]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALIA SABUR whose telephone number is (571)270-7219. The examiner can normally be reached M-F 9:30-5:30.
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/ALIA SABUR/Primary Examiner, Art Unit 2812
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