Prosecution Insights
Last updated: September 20, 2026
Application No. 18/742,173

WAFER PROCESSING METHOD

Non-Final OA §102§103
Filed
Jun 13, 2024
Priority
Jul 04, 2023 — JP 2023-109814
Examiner
BRECHT, CHARLES MATTHEW
Art Unit
Tech Center
Assignee
DISCO Corporation
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds

Examiner Intelligence

Grants only 0% of cases
0%
Career Allowance Rate
0 granted / 0 resolved
-60.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
Avg Prosecution
39 currently pending
Career history
24
Total Applications
across all art units
This examiner has no resolved cases yet (career too new); statute-level performance unavailable. The Grant Probability card shows Tech Center averages instead.

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (2022/0336221, hereafter Lee). Regarding claim 1, Lee discloses a wafer processing method for processing a wafer (11, Fig. 1) having an effective region (13d_1; Fig. 1, 3, par. 0028) formed on a top surface of the wafer and a chamfered portion (13a_1; Fig. 1, par. 0026) at an outer circumference of the wafer, the chamfered portion surrounding the effective region, the method comprising: a modified layer forming step of forming a modified layer (13e_1, Fig. 4, par. 0040) along the chamfered portion by applying a laser beam (L, Fig. 4) having a wavelength transmissible through the wafer (par. 0033) with a condensing point of the laser beam positioned in an inner part of a boundary portion (17, Fig. 3, par. 0034) between the effective region and the chamfered portion; a chamfered portion removing step of scattering and removing the chamfered portion by a centrifugal force by holding the wafer on a spinner table (4, Fig. 4) and rotating the wafer at high speed after the modified layer forming step is performed (par. 0053, 0058); and a processing step of processing the wafer to thin the wafer to a desired thickness by grinding an undersurface (13b, Fig. 7, par. 0054, 0057) of the wafer after the chamfered portion removing step is performed. Regarding claim 2, Lee discloses a wafer processing method wherein the modified layer forming step includes a first step of forming such a relatively deep first modified layer (13e_1, Fig. 4) that a crack (13f, Fig. 4, par. 0040) reaches the top surface (13a, Fig. 4) of the wafer, by applying the laser beam (L, Fig. 4, par. 0035) with the condensing point of the laser beam positioned in the inner part of the boundary portion (17, Fig. 3, par. 0035) between the effective region (13d_1, Fig. 3 – 4) and the chamfered portion (13a_1, Fig. 4), and a second step of forming a relatively shallow second modified layer (13e_2; Fig. 5) that is outwardly or inwardly adjacent to the first modified layer and that does not reach the top surface (par. 0047-0048), and the chamfered portion is warped (Fig. 4 - 5) from the effective region to the undersurface side (13b, Fig. 4 – 5) with the first modified layer as a starting point (Fig. 3, par. 0042). Regarding claim 3, Lee discloses a wafer processing method wherein the wafer (11, Fig. 1) is a bonded wafer formed by bonding a first wafer (13, Fig. 1) and a second wafer (15, Fig. 1) to each other, and the modified layer forming step, the chamfered portion removing step, and the processing step are performed on the first wafer (Figs. 4 – 7, par. 0029, 0054, 0058). Regarding claim 4, Lee discloses a wafer processing method wherein, in the second step, the second modified layer (13e_2, Fig. 5) is formed at a position (13d_2, Fig. 5, 7; par. 0054) to be ground and removed in the processing step. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Katoh et al. (2008/0214094, hereafter Katoh). Regarding claim 5, Lee, discussed above, fails to disclose a wafer processing method wherein, in the chamfered portion removing step, a rotational speed of the spinner table is 1000 to 3000 rpm. However, Katoh teaches a wafer processing method wherein, in the chamfered portion removing step, a rotational speed of the spinner table is 1000 to 3000 rpm (par. 0066). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Katoh by utilizing a rotational speed of 1000 to 3000 rpm in order to provide the necessary centrifugal force that is used for debris removal to separate the chamfered edge from the wafer. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M BRECHT whose telephone number is (571)272-9634. The examiner can normally be reached Mon-Fri: 7:30am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (572) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.M.B./ Examiner, Art Unit 2817 /ALI NARAGHI/ Primary Examiner, Art Unit 2817
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Prosecution Timeline

Jun 13, 2024
Application Filed
Aug 18, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allowance rate.

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