DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of species A, fig. 1, claims 1-5, 7-13 and 15-19 in the reply filed on 8/10/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 6, 14 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/10/26.
Allowable Subject Matter
Claims 16-19 are allowed.
Claims 2, 3, 10 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, 7-9, 13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh et al., US 20240170046 A1 in view of Yamamoto, US 20170140812 A1.
Yeh teaches:
1. An integrated circuit (IC) device comprising (see fig. 3 annotated below, including an enlarged view):
PNG
media_image1.png
347
880
media_image1.png
Greyscale
PNG
media_image2.png
944
840
media_image2.png
Greyscale
first and second bit circuits adjacent to each other along a row direction (e.g. first and second bit circuits in top row annotated in fig. 3);
third and fourth bit circuits adjacent to each other along the row direction (e.g. third and fourth bit circuits in bottom row annotated in fig. 3); and
a first column of output pins (e.g. plurality of GL1, GL2) aligned in a column direction, wherein
the first and second bit circuits comprise:
first through fourth power rails extending in the row direction (e.g. rails of RL1_1, RL1_2, see power rails #1-4 annotated in fig. 3. Note rails RL1_1, RL1_2 extend horizontally and then vertically along RL1_1, RL2_1 because they are coupled at VA!, VA2.); and
first through sixth active areas (e.g. see Remarks below) extending in the row direction,
the third and fourth bit circuits comprise:
the fourth power rail and fifth through seventh power rails extending in the row direction (e.g. rails of RL1_1, RL1_2, RL2_1, RL2_2, see power rails #4-7 annotated in fig. 3. Note rails RL1_1, RL1_2 extend horizontally and then vertically along RL1_1, RL2_1 because they are coupled at VA!, VA2) ; and
seventh through twelfth active areas (e.g. see Remarks below) extending in the row direction, and
the first column of output pins comprises:
first and second output pins (e.g. plurality of GL1, GL2) adjacent to the second bit circuit and coupled to the respective first and second bit circuits; and
third and fourth output pins (e.g. plurality of GL1, GL2) adjacent to the fourth bit circuit and coupled to the respective third and fourth bit circuits. See Yeh at para. [0001] – [0051], figs. 1-8.
Regarding claim 1:
Yeh is silent:
the first and second bit circuits comprise:
first through sixth active areas extending in the row direction,
the third and fourth bit circuits comprise:
seventh through twelfth active areas extending in the row direction
However, it would have been obvious to one of ordinary skill in the art that in Yeh’s fig. 1, “the first and second bit circuits comprise:
first through sixth active areas extending in the row direction,
the third and fourth bit circuits comprise:
seventh through twelfth active areas extending in the row direction”
because Yeh teaches the memory blocks MCA1 having circuit areas 111, 112.
Furthermore, in an analogous art, Yamamoto teaches:
(see fig. 1) A memory cell (MC) comprises six transistors (QL1, QL2, QT1, QT2, QD!, QD2) and each transistor comprises at least three active areas such as source, drain and gate. The memory cell (MC) stores one bit of data. See Yamamoto at para. [0030] – [0033].
One of ordinary skill in the art modifying Yeh with Yamamoto to form a memory bit circuit comprising six transistors will form “first through sixth active areas extending in the row direction” and “seventh through twelfth active areas extending in the row direction” as recited in the claim.
Regarding claim 5:
Yeh teaches all the limitations of claim 1 above, but does not expressly teach fifth to eight bit circuits.
However, it would have been obvious to one of ordinary skill in the art to form fifth to eight bit circuits because this involves duplicating the 2x2 array to form a larger 4x2 array as shown below. Duplication of essential working parts of a device involve only routine skill in the art. See MPEP 2144.04, Legal Precedent as Source of Supporting Rationale, VI. Reversal, Duplication, or Rearrangement of Parts.
Furthermore, Yamamoto teaches “The input/output terminals of this pair of CMOS inverters (storage nodes VL and VR) are cross-linked to configure a flip-flop circuit as a data storage to store one bit of data.” See Yamamoto at [0033].
Thus, one of ordinary skill in the art would be motivated to form a larger 4x2 array in order to configure additional flip flop circuits to store additional bits of data.
One of ordinary skill in the art forming a 4x2 array would arrive at the claimed limitation “further comprising: fifth and sixth bit circuits adjacent to each other along the row direction; and seventh and eighth bit circuits adjacent to each other along the row direction, wherein the fifth and sixth bit circuits comprise: the seventh power rail and eighth through tenth power rails extending in the row direction; and thirteenth through eighteenth active areas extending in the row direction, the seventh and eighth bit circuits comprise: the tenth power rail and eleventh through thirteenth power rails extending in the row direction; and nineteenth through twenty-fourth active areas extending in the row direction, and the first column of output pins further comprises: fifth and sixth output pins adjacent to the sixth bit circuit and coupled to the respective fifth and sixth bit circuits; and seventh and eighth output pins adjacent to the eighth bit circuit and coupled to the respective seventh and eighth bit circuits.”
PNG
media_image2.png
944
840
media_image2.png
Greyscale
FORMING 4x2 ARRAY
PNG
media_image3.png
944
840
media_image3.png
Greyscale
Regarding claim 7:
Yamamoto further teaches:
7. The IC device of claim 1, wherein the IC device comprises a multi-bit flip-flop circuit, and each of the first through fourth bit circuits comprises a flip-flop bit circuit, para. [0033].
Regarding claim 8:
Yeh further teaches:
8. The IC device of claim 1, wherein each of the first through fourth bit circuits comprises an input pin (e.g. plurality of GL1, GL2), fig. 3.
Regarding claim 9:
Yeh and Yamamoto teach the limitations as applied to claims 1 and 7 above.
Regarding claim 13:
Yeh teaches the limitations as applied to claim 5 above.
Regarding claim 15:
Yeh teaches the limitations as applied to claim 8 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Yeh with the teachings of Yamamoto because a SRAM memory cell comprises six transistors coupled together and “The input/output terminals of this pair of CMOS inverters (storage nodes VL and VR) are cross-linked to configure a flip-flop circuit as a data storage to store one bit of data.” See Yamamoto at para. [0031], [0033].
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh in view of Yamamoto, as applied to claims 1 and 9 above, in further view of Vogley et al., US 5982694 A.
Regarding claim 4:
Yeh and Yamamoto teach all the limitations of claim 1 above, but do not expressly teach:
4. The IC device of claim 1, wherein each of the first through fourth bit circuits is coupled to a same clock signal path.
In an analogous art, Vogley teaches a plurality of bit circuits coupled to a same clock path (CLK). See Vogley at col 10, ln 55–67, col 7, ln 1–15.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Yeh with the teachings of Vogley because the same clock path enables synchronuous action to minimize propagation delay.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh in view of Yamamoto, US 20170140812 A1, as applied to claims 1 and 9 above, in further view of Manning, US 6301322 B1.
Regarding claim 12:
Yeh and Yamamoto teach all the limitations of claim 1 above, but do not expressly teach:
12. The IC device of claim 9, further comprising: a pair of clock paths electrically connected to each of the first through fourth bits.
In an analogous art, Manning teaches a pair of clock paths (CLK, CLK90) electrically connected to bits in figs. 3 and 6. See Manning at col 6, ln 1–67, col 8, ln 45–67, col 9, ln 1–29.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Yeh with the teachings of Manning because “A bit shifting circuit having shifting operations with a more balanced duty cycle includes both a clock circuit and shift register. The clock circuit produces two sets of complementary clock signals from two input clock signals, where the clock transitions of the non-inverted and inverted clock signals of each set have a low-skew, or aligned clock edges.” See Manning at col 5, ln 25-35.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Michele Fan/
Primary Examiner, Art Unit 2818
9 October 2026
Prosecution Insights