DETAILED ACTION
This action is responsive to Remarks and Claim Amendments filed on August 17, 2026.
Claims 1, 9-10, 13 and 15 have been amended.
Claims 1-19 are pending and are presented to examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Response to Amendments
The amendment to the abstract, replacing A parallel burning system and method are disclosed with A parallel burning system and method is disclosed, is acknowledged and entered. The objection to the specification under MPEP § 608.01(b) is withdrawn.
The objection to claim 9 for informalities is withdrawn. Claim 9 has been amended to recite a battery management unit (BMU) of a pack, which places the acronym in parentheses as required.
The objection to the drawings is maintained, and a further ground of objection is added as necessitated by Applicant's amendment. Applicant asserts that all of the rectangular boxes shown in Figure 1 of the as-filed drawings are already labeled. That assertion is not persuasive. The boxes of Figure 1 bear reference numerals only; a reference numeral identifies a part for cross-reference to the written description, but it is not a descriptive legend and it does not convey what the box represents. The full objection is restated in the Drawings section below.
The rejection of claims 1–9 under 35 U.S.C. 101 is withdrawn. Claim 1 has been amended to recite that the master host computer comprising a processor and a memory, that each of the plurality of slave host computers comprises a processor and a memory, and that each of the plurality of burning modules comprises physical circuitry to perform burning operations. These recitations tie the claimed elements to tangible structure, and the claim no longer reads on software per se under MPEP § 2106.03(II).
The rejection of claims 13 and 15–17 under 35 U.S.C. 112(b) is withdrawn. Claim 13 has been amended to recite the product number, which finds antecedent basis in claim 10. Claim 15 has been amended to depend from claim 12, which introduces a first verification, so that the ordinal qualifier in a second verification is no longer without antecedent within claim 15's dependency chain. Claims 16 and 17 inherit the corrected chain and are no longer rejected on the inherited ground.
The rejection of claim 18 under 35 U.S.C. 112(b) is withdrawn in part and maintained in part. Grounds (i) and (ii) of the prior rejection are withdrawn because the amendment to claim 15 supplies the missing antecedents through the chain claim 10 → claim 11 → claim 12 → claim 15 → claim 18. Ground (iii) is maintained and is restated in full below.
The rejections under 35 U.S.C. 102 and 103 set forth in the non-final Office action are withdrawn and are replaced by the new grounds of rejection set forth below, which are necessitated by Applicant's amendment.
Response to Arguments
Applicant's arguments filed in reply to the non-final Office action have been fully considered and are addressed below.
Applicant argues that the bus interface circuits of Jin (IIC, SPI, PSOC, PIC, CPLD, or BIOS) are data transmission pathways between the slave MCUs and the chips being programmed, that they facilitate the transfer of burning data but do not themselves perform burning operations or possess burning functionality, and that the burning operations in Jin are performed by the slave MCUs. Applicant concludes that Jin does not disclose or fairly suggest the plurality of slave host computers are connected one to one with the plurality of burning modules.
This argument is persuasive as directed to the grounds of rejection set forth in the non-final Office action, and those grounds are withdrawn. The Examiner no longer maps the recited burning modules onto the bus interface circuits of Jin. The rejections below rely on White as the primary reference. White discloses a pin driver circuit that is a structurally separate element from the site processor that commands it, and that develops and applies the programming voltages and waveforms to the pins of the device being programmed. Applicant's argument is therefore moot as to the present grounds.
Applicant's argument does, however, contain an admission that supports the present grounds. At page 12 of the Remarks, Applicant states that Jin at most discloses a parallel burning system used to burn chips of different bus types, and enumerates those bus types as Inter Integrated Circuit (IIC), Serial Peripheral Interface (SPI), Programmable System Of Chip (PSOC), Priority Interrupt Control (PIC), Complex Programmable Logic Device (CPLD), and Basic Input Output System (BIOS). Applicant further characterizes those bus types as defining communication interfaces through which data is transmitted. Jin is relied upon in the rejections below solely for the limitation the plurality of burning modules are connected to a plurality of products to be burned by using different communication modes. Applicant's own characterization of Jin confirms that Jin teaches the use of different communication modes to reach the devices being programmed, and Applicant advances no argument against that narrower use of Jin.
Applicant argues that amended claim 1 is allowable because it recites each of the plurality of burning modules comprises physical circuitry to perform burning operations, and that none of the cited references disclose or suggest this feature. This argument is not persuasive as to the present grounds. As set forth below, White discloses a pin driver circuit 204 that is coupled to the receptacle 205 holding the device under test and that develops the appropriate voltages and waveforms on the appropriate pins of the device under test according to the device manufacturer's specifications (White, column 4 lines 40-63, column 4 line 64 – column 5 line 11, column 8 lines 30-46). Developing and applying the programming voltages and waveforms to the pins of a device is the physical act by which operating code is written into that device. The present specification at ¶[0105] expressly provides that a burning module may be a burner, a burning circuit, a burning board, a burning device, and other modules having burning functions, which is not limited, and White's pin driver circuit is a burning circuit within that express definition.
Applicant argues that independent claim 10, as amended, includes limitations similar to those of claim 1 and is distinguishable for the same reasons, and that the dependent claims are allowable for at least the same reasons. Because the arguments directed to claim 1 are not persuasive as to the present grounds, the arguments directed to claim 10 and to the dependent claims are likewise not persuasive.
Drawings
Figures 1 and 2 are objected to. The grounds of objection applicable to each figure are set forth below.
Figures 1 and 2 are objected to under 37 CFR 1.84(o) because they contain unlabeled rectangular boxes that should be provided with descriptive text labels. In Figure 1, each of the boxes designated 11, 13, 16, and 17, each of the boxes 121, 122, and 123 within the group designated 12, each of the boxes 141, 142, and 143 within the group designated 14, and each of the boxes 151, 152, and 153 within the group designated 15, contains a reference numeral and no other content. In Figure 2, each of the boxes designated 20, 21, 22, 23, and 24 likewise contains a reference numeral and no other content. The only textual matter appearing in Figure 1 is the legend in the lower left portion of the sheet identifying the solid arrow as Call and the double line as Communication, which describes the connections between the boxes and not the boxes themselves.
A reference numeral is not a descriptive legend. Under 37 CFR 1.84(o), suitable descriptive legends may be required by the examiner where necessary for understanding of the drawing. Descriptive legends are necessary here because Figure 1 is the sole figure depicting the overall architecture of the claimed system, and as presently drawn a reader cannot determine from the figure which box corresponds to the master host computer, which corresponds to the slave host computers, which corresponds to the multi-channel control module, which corresponds to the burning modules, which corresponds to the products to be burned, or which corresponds to the burning file management system, without leaving the drawing and consulting the written description. Applicant's own drawing set confirms that descriptive legends are both practicable and expected in this application: Figures 3, 4, 5, 7, and 8 each place descriptive text inside the boxes, and Figure 7 in particular labels its boxes with the terms Master host computer, Slave host computer 1, Boot burning 1, and App burning 1. Figure 1 should be provided with corresponding descriptive text labels.
Figure 1 is further objected to under 37 CFR 1.83(a) because it fails to show the following features specified in the claims: a processor and a memory of the master host computer; a processor and a memory of each of the plurality of slave host computers; and physical circuitry of each of the plurality of burning modules. Amended claim 1 recites the master host computer comprising a processor and a memory, each of the plurality of slave host computers comprises a processor and a memory, and each of the plurality of burning modules comprises physical circuitry to perform burning operations. The drawing in a nonprovisional application must show every feature of the invention specified in the claims, and any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. See MPEP § 608.02(d); form paragraph 6.22.01. Figure 1 depicts the box 11, the boxes 121, 122, and 123, and the boxes 141, 142, and 143 as undifferentiated rectangles containing no internal structure, and therefore does not show the recited processor, memory, or physical circuitry. This ground of objection is necessitated by Applicant's amendment, which introduced these structural recitations into claim 1.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to this Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either Replacement Sheet or New Sheet pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, Applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitations performing a third verification on the products to be burned in the plurality of packs and data identifiers of the burning data corresponding to the products to be burned in the plurality of packs. The plurality of packs is established in parent claim 15, which recites assembling the plurality of burned products to obtain a plurality of packs. The packs recited in claim 18 are therefore, by the terms of claim 15, formed from products that have already been burned. Claim 18 nonetheless applies the qualifier to be burned to those same products while they are inside the assembled packs.
Within the dependency chain of claim 18 (claim 10 → claim 11 → claim 12 → claim 15 → claim 18), claims 10, 11, and 12 recite products to be burned, claim 15 recites burned products, and claim 18 reverts to products to be burned for articles that claim 15 has already placed inside packs assembled from burned products. Nothing in the claims or the specification establishes whether these two terms denote the same physical articles at different temporal stages of the manufacturing flow, or instead denote a fixed class of articles independent of burning state. A person of ordinary skill in the art cannot determine which reading claim 18 requires, and therefore cannot determine the metes and bounds of claim 18, with reasonable certainty. Nautilus, Inc. v. Biosig Instruments, Inc., 572 U.S. 898, 910 (2014).
For purposes of examination, the Examiner interprets the products to be burned in the plurality of packs, as recited twice in claim 18, to mean the burned products contained in the plurality of packs obtained in claim 15, that is, the same physical articles recited as the plurality of burned products in claim 15. The prior art is applied to claim 18 below on that interpretation. Amendment of claim 18 to recite the burned products in the plurality of packs, consistent with the terminology of claim 15, would overcome this rejection.
No claim other than claim 18 is rejected under 35 U.S.C. 112(b) in this Office action. No claim depends from claim 18, so no claim is rejected under this section solely as inheriting the indefiniteness of a base claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 7, 8, 10, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over White (US Pat. No. 6,351,774, hereinafter “White”) in view of Jin et al. (US Pub. No. 2009/0089469, hereinafter “Jin” – previously presented).
With respect to claim 1 (Currently Amended), White teaches A parallel burning system, comprising a master host computer, a plurality of slave host computers, and a plurality of burning modules (White, Abstract; column 2 lines 39-54; column 3 lines 27-37, column 4 lines 40-63). White discloses a concurrent programming system S comprising a plurality of programming sites 100 each connected to a central controller 102, the programming sites being grouped into a programming station 104 (White, column 3 lines 27-37). The central controller 102 is the recited master host computer, the plurality of programming sites 100 are the recited plurality of slave host computers, and the pin driver circuit 204 within each programming site is the recited burning module, as detailed below. White expressly characterizes the operation performed by the system as burning, stating that the computer controlled group of programmer sites is provided to burn in or enter operating code into various types of programmable electronic devices (White, Abstract), and that users program devices by transferring or burning in a sequence of operating codes into the memory (White, column 1 lines 16-24). The system is parallel in that the sites operate concurrently, as addressed below.
wherein the master host computer comprising a processor and a memory is connected to the plurality of slave host computers (White, column 3 lines 27-37, column 3 lines 38-56; column 2 lines 39-64). White discloses that the central controller 102 is conveniently a conventional International Business Machines (IBM) compatible personal computer (PC) including a display 106 and input device 108, and that other standard or proprietary computers capable of remote communications and user interaction may be used (White, column 3 lines 38-56). A personal computer necessarily comprises a processor and a memory; White further confirms the presence of memory in the central controller by disclosing that a data pattern is selected and loaded into a buffer of the central controller 102 (White, column 5 lines 26-45) and that the central controller memorizes or stores the optimized sequence in its memory (White, column 5 line 46 – column 6 line 24). As to the connection, White discloses that the central controller 102 connects to the programming sites 100 via a bidirectional parallel port, although any serial or parallel communications scheme is adequate, and that in an alternative embodiment the programming stations 104 are connected to a conventional computer network, such as Ethernet or Token Ring, with each programming site 100 being a network node (White, column 3 lines 38-56).
the plurality of slave host computers are connected one to one with the plurality of burning modules, constituting a plurality of burning channels (White, column 3 lines 27-37, column 4 lines 40-63, column 4 line 64 – column 5 line 11). White discloses that each programming site 100 includes identical logic and features (White, column 3 lines 57-67), and that within a programming site 100 a central processing unit (CPU) 200 couples to memory 202, a pin driver circuit 204, an output port 206, an input port 208 and a communications interface 210 (White, column 4 lines 40-63). Each programming site therefore contains exactly one CPU 200 and exactly one pin driver circuit 204, so that the CPUs and the pin driver circuits are equal in number and are paired one with one. The pin drivers 204 are coupled to an interchangeable receptacle or socket 205 for applying voltages and waveforms to a device under test (DUT) 224 received into the receptacle 205 (White, column 4 line 64 – column 5 line 11). Each resulting path from a CPU 200, through its pin driver circuit 204, to the DUT 224 held in its receptacle 205 is a burning channel by which burning data reaches one product, and the plurality of such paths across the plurality of sites constitutes the recited plurality of burning channels.
each of the plurality of slave host computers comprises a processor and a memory (White, Abstract; column 2 lines 39-54; column 4 lines 40-63). White discloses that each programmer site includes its own computer processor or CPU (White, Abstract), that the present invention provides a control computer and a suitable number of programming sites, each of which includes its own computer (White, column 2 lines 39-54), and that a central processing unit (CPU) 200 couples to memory 202 within the programming site 100 (White, column 4 lines 40-63). White further discloses that the programming site 100 receives the control sequence from the central controller 102 and stores it in memory 202, and that a shared memory or direct memory access (DMA) architecture may alternatively be used wherein each programming site 100 includes a CPU 200 that communicates with the shared memory module (White, column 4 lines 40-63).
each of the plurality of burning modules comprises physical circuitry to perform burning operations (White, column 4 lines 40-63, column 4 line 64 – column 5 line 11, column 8 lines 12-46). White discloses that the programming site 100 includes a pin driver circuit 204 — expressly a circuit, and a structurally distinct element from the CPU 200 that couples to it (White, column 4 lines 40-63). White further discloses that the pin drivers 204 are coupled to an interchangeable receptacle or socket 205 for applying voltages and waveforms to a device under test (DUT) 224 received into the receptacle 205, that the DUT 224 is the programmable device currently being operated on by the programming site 100, and that the CPU 200 executes the control sequence, thereby causing the pin drivers 204 to develop appropriate voltages and waveforms on appropriate pins of the DUT according to the device manufacturer's specifications of the DUT (White, column 4 line 64 – column 5 line 11). White additionally discloses that the CPU 200 adjusts its programming parameters, such as programming voltages and pulse widths, which the pin drivers then apply to the device (White, column 8 lines 31-46). The development and application of the programming voltages and waveforms onto the pins of the device is the physical act by which the operating code is written into the device; the pin driver circuit 204 is therefore physical circuitry that performs burning operations. This mapping is consistent with the express definition of a burning module in the present specification at ¶[0105], which provides that the burning module may be a burner, a burning circuit, a burning board, a burning device, and other modules having burning functions, which is not limited.
the master host computer is used to call the plurality of slave host computers to transmit multiple pieces of burning data corresponding to the plurality of products to be burned to the plurality of burning modules via the plurality of burning channels (White, column 5 line 26 – column 6 line 24, column 6 line 54-67, column 7 lines 13-35). White discloses that the central controller 102 proceeds to download executable code to each of the programming sites 100, at step 306, and that after the executable code is downloaded, at step 308, the central controller 102 downloads the data pattern to be programmed into the selected devices to each of the programming sites 100 (White, column 5 lines 26-45). White further discloses that the central controller 102 downloads the memorized sequence to each of the programming sites 100 at step 314 (White, column 5 line 46 – column 6 line 24), and that the central controller 102 then enables each of the programming sites 100 for independent operation, step 318, thereby causing each site to execute steps 400–418 (White, column 6 lines 54-67). Each site's CPU 200 then executes those steps, and at step 406 the device is programmed according to the downloaded sequence of instructions and particular device characteristics (White, column 7 lines 13-35), the programming being effected through that site's pin driver circuit 204 (White, column 4 line 64 – column 5 line 11). The central controller thus calls each programming site to transmit its respective burning data to that site's pin driver circuit by way of that site's burning channel.
and burn the multiple pieces of burning data in parallel by means of the plurality of burning modules to the plurality of products to be burned (White, Abstract; column 4 lines 1-18, column 4 lines 25-39, column 7 lines 13-35). White discloses that thereafter, each programmer site, including the former master site, operates autonomously to program the devices independently of the status of the other sites (White, Abstract), and that from then on the programming sites 100 operate independently and concurrently to program individual programmable devices of the same type without intervention from the central controller 102 (White, column 4 lines 1-18). White further discloses that each of the programming sites 100 is capable of performing this sequence of steps independently and concurrently with the other sites (White, column 7 lines 13-35), and quantifies the resulting parallelism by disclosing that prior art programmers were limited to about 88 devices per hour whereas by providing multiple independent programming sites throughput can be increased to about 700 devices per hour (White, column 4 lines 25-39). The burning of the multiple pieces of burning data therefore occurs in parallel by means of the plurality of pin driver circuits to the plurality of devices under test.
White is silent to disclose; however, in an analogous art, Jin teaches the plurality of burning modules are connected to a plurality of products to be burned by using different communication modes (Jin, Title; Abstract; ¶[0025], ¶[0026], ¶[0030]). Jin discloses a parallel burning system for burning chips of various types, in which a master micro controller unit 20 distributes the configuration and program data to slave micro controller units 30a, 30b, which in turn burn their respective chips (Jin, ¶[0025], ¶[0026]). Jin expressly discloses that the bus type for the chip to be burned can be one of various types of buses, enumerating the Inter Integrated Circuit (IIC) type, the Serial Peripheral Interface (SPI) type, the Programmable System Of Chip (PSOC) type, the Priority Interrupt Control (PIC) type, the Complex Programmable Logic Device (CPLD) type, and the Basic Input Output System (BIOS) type (Jin, ¶[0030]). Each such bus type is a distinct communication mode by which burning data is conveyed to the chip being programmed, so that the elements that deliver burning data to the chips are connected to those chips by using different communication modes. Applicant concedes this teaching at page 12 of the Remarks.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have modified the concurrent programming system of White so that the pin driver circuits are connected to the devices being programmed by using the different bus-type communication modes taught by Jin. One of ordinary skill would have been motivated to do so because White expressly teaches that each programming site is capable of programming a variety of programmable devices, such as Programmable Logic Devices (PLDs), Programmable Array Logic (PAL) devices, Programmable Read-Only Memories (PROMs, OTP PROMs, EPROMs, EEPROMs, FLASH memories, etc.), Field Programmable Gate Arrays (FPGAs), programmable microcontrollers and other devices containing a programmable element, with all types of package types supported by an interchangeable receptacle (White, column 3 lines 57-67), and further contemplates that the programming station 104 could be initialized to concurrently program different device types (White, column 4 lines 1-18) — device types that, as Jin teaches, require different bus protocols (Jin, ¶[0030]). Supplying the different bus-type communication modes of Jin would allow White's system to realize the mixed-device-type capability White itself contemplates, and would avoid the alternative of integrating multiple separate programmers, which the art recognizes as expensive and as creating interference between the programmers. The combination is the application of a known technique, Jin's support for multiple bus types, to a known device ready for improvement, White's multi-site concurrent programmer, to yield the predictable result of concurrently programming devices of differing bus types. With respect to claim 7 (Original), White is silent to disclose; however, in an analogous art, Jin teaches the system further comprises a burning file management system (Jin, ¶[0026]; FIG. 1). Jin discloses a computer 10 that supplies the configuration information used to drive the parallel burning operation, and that is a component of the disclosed burning system alongside the master micro controller unit 20 and the slave micro controller units 30a, 30b (Jin, ¶[0026]).
the burning file management system is deployed on a computer device other than the master host computer, and establishes a communication connection with the master host computer (Jin, ¶[0026]; FIG. 1). Jin discloses that the computer 10 is a device separate and distinct from the master micro controller unit 20, and that the computer 10 is communicatively coupled to the master micro controller unit 20 through the hub 60 (Jin, ¶[0026]). The computer 10 is therefore deployed on a computer device other than the element mapped to the master host computer and establishes a communication connection with it.
the burning file management system is configured to store data corresponding to the plurality of products to be burned (Jin, ¶[0026], ¶[0030]). Jin discloses that the computer 10 holds, for each chip to be burned, the chip type, the bus type of that chip, and the program data to be written into that chip, and supplies that per-chip information to the master micro controller unit 20 (Jin, ¶[0026], ¶[0030]). That per-chip information is data corresponding to each of the plurality of products to be burned.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have modified the system of White in view of Jin to include a separate computer device holding the programming files and communicating with the central controller, as taught by Jin. One of ordinary skill would have been motivated to do so because White expressly teaches that a number of programming stations 104 can be connected to the central controller 102 if further capacity is desired, and that the programming stations may be connected to a conventional computer network such as Ethernet or Token Ring with each programming site 100 being a network node (White, Detailed Description (2), (3)), so that a networked file repository serving multiple stations is a natural extension of White's own architecture. Locating the programming files on a separate networked computer device, as Jin teaches, would allow the files to be revised, versioned, and served centrally without taking the production controller offline, and would allow multiple controllers to draw from a single authoritative set of per-product programming data, thereby reducing the risk that different stations program from inconsistent file copies.
With respect to claim 8 (Original), White teaches wherein the master host computer is connected to the plurality of slave host computers by using the same communication mode (White, column 3 lines 27-56). White discloses that the central controller 102 connects to the programming sites 100 via a bidirectional parallel port, although any serial or parallel communications scheme is adequate (White, column 3 lines 38-56). A single bidirectional parallel port serving all of the programming sites is a single, common communication mode used for every site. White discloses in the alternative that the programming stations 104 are connected to a conventional computer network, such as Ethernet or Token Ring, with each programming site 100 being a network node (White, column 3 lines 38-56); a single network protocol shared by all nodes is likewise a single, common communication mode used for every site. Either embodiment discloses connecting the central controller to the plurality of programming sites by using the same communication mode. This is to be distinguished from the connection between the burning modules and the products to be burned recited in claim 1, which uses different communication modes.
With respect to claim 10 (Currently Amended), the claim recites a method that is the method of operation of the system of claim 1, and recites limitations similar to claim 1. The mappings of the master host computer to the central controller 102 of White, of the plurality of slave host computers to the plurality of programming sites 100 of White, and of the plurality of burning modules to the pin driver circuits 204 of White, as set forth above with respect to claim 1, apply equally to claim 10 and are relied upon here.
White teaches A parallel burning method applied to a master host computer in a parallel burning system, the system further comprising a plurality of slave host computers and a plurality of burning modules (White, Abstract; column 2 lines 39-54; column 3 lines 27-37, column 4 lines 40-63), for the reasons set forth above with respect to the corresponding limitation of claim 1.
White teaches determining, based on product numbers of a plurality of products to be burned, multiple pieces of burning data corresponding to the plurality of products to be burned (White, column 5 line 26 – column 6 line 24, column 8 lines 12-29). White discloses that initialization of the central controller 102 includes selecting the device type and selecting a data pattern to be programmed into the programmable devices and loading it into a buffer of the central controller 102 (White, column 5 lines 26-45), so that the burning data is selected as a function of the identity of the device to be programmed. White further discloses that the central controller 102 checks each programming site 100 for the correct configuration, including checking for the proper receptacle 205 and whether it is installed correctly (White, column 5 lines 26-45), and that at step 502 a device identifier is read from the device 224, the device identifier providing device specific information which can vary from particular devices of the same type and even from the same manufacturer, such as required programming voltages and programming pulse widths (White, column 8 lines 12-29). The device type designation and the device identifier read from each device are product numbers of the products to be burned within the broadest reasonable interpretation of that term, and the corresponding data pattern and programming parameters determined from them are the multiple pieces of burning data corresponding to the plurality of products to be burned.
White teaches calling the plurality of slave host computers to transmit the multiple pieces of burning data to the plurality of burning modules via a plurality of burning channels constituted after the plurality of slave host computers are connected one to one with the plurality of burning modules (White, column 4 line 40 – column 5 line 11, column 5 line 26 – column 6 line 24, column 6 lines 54-67, column 7 lines 12-35), for the reasons set forth above with respect to the corresponding limitations of claim 1. In particular, the central controller 102 downloads the executable code at step 306 and the data pattern at step 308 to each of the programming sites 100 (White, column 5 lines 26-45), downloads the memorized sequence to each site at step 314 (White, column 5 line 46 – column 6 line 24), and enables each site for independent operation at step 318 (White, column 6 lines 54-67), whereupon each site's CPU 200 executes the control sequence and causes its pin driver circuit 204 to apply the programming data to the device in its receptacle 205 (White, column 4 line 64 – column 5 line 11, column 7 lines 13-35). The one-to-one pairing of the CPU 200 and the pin driver circuit 204 within each programming site 100, and the burning channels so constituted, are as set forth above with respect to claim 1.
White teaches and burning the multiple pieces of burning data in parallel by means of the plurality of burning modules to the plurality of products to be burned, wherein the plurality of burning modules perform burning operations (White, Abstract; column 4 lines 1-18, column 4 lines 25-39, column 4 line 64 – column 5 line 11, column 7 lines 13-35, column 8 lines 30-45). The parallel burning is as set forth above with respect to the corresponding limitation of claim 1. As to the final clause, White discloses that the CPU 200 executes the control sequence, thereby causing the pin drivers 204 to develop appropriate voltages and waveforms on appropriate pins of the DUT according to the device manufacturer's specifications of the DUT (White, column 4 line 64 – column 5 line 11), and that the CPU 200 adjusts its programming parameters, such as programming voltages and pulse widths, which are then applied by the pin drivers (White, column 8 lines 30-45). The pin driver circuits therefore perform the burning operations as recited.
White is silent to disclose; however, in an analogous art, Jin teaches: establishing a connection between the plurality of burning modules and the plurality of products to be burned by using different communication modes (Jin, Title; Abstract; ¶[0025], ¶[0026], ¶[0030]). Jin discloses that the bus type for the chip to be burned can be one of various types of buses, enumerating the Inter Integrated Circuit (IIC) type, the Serial Peripheral Interface (SPI) type, the Programmable System Of Chip (PSOC) type, the Priority Interrupt Control (PIC) type, the Complex Programmable Logic Device (CPLD) type, and the Basic Input Output System (BIOS) type (Jin, ¶[0030]), and that the elements which deliver the burning data reach their respective chips over those buses (Jin, ¶[0025], ¶[0026]). Establishing the connection over a respective one of those bus types is establishing a connection by using different communication modes.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have modified the concurrent programming method of White so that the connection between the pin driver circuits and the devices being programmed is established by using the different bus-type communication modes taught by Jin, for the same reasons set forth above with respect to claim 1, namely, to realize within a single concurrent programming run the mixed-device-type capability that White itself contemplates (White, column 3 line 57 – column 4 line 18) for device types that, as Jin teaches, require different bus protocols (Jin, ¶[0030]), and to avoid the expense and mutual interference that the art associates with integrating multiple separate programmers.
With respect to claim 14 (Original), White teaches determining preset burning items and burning steps corresponding to each of the plurality of products to be burned (White, column 5 line 26 – column 6 line 24, column 8 lines 12-45). White discloses that initialization includes selecting the device type; selecting a data pattern to be programmed into the programmable devices and loading it into a buffer of the central controller 102; selecting a number of operations to be performed; and selecting various other options including word range, offset, data path width, blank checking, verification after programming, continuity testing, autostart, check electronic ID, run vector tests, and security programming (White, column 5 lines 26-45). Those selected options are preset burning items. White further discloses that the central controller 102 communicates a sequence of commands to the master site 100a, that as the master site performs the commands the central controller memorizes or stores the sequence in its memory, and that it is desirable that only necessary steps are memorized, thereby providing a more efficient or optimized sequence of steps for the sites 100 to subsequently execute (White, column 5 lines 26-45). That memorized sequence is the burning steps. White additionally discloses that a device identifier is read from the device 224 which provides device specific information, such as required programming voltages and programming pulse widths, that can vary from particular devices of the same type (White, column 8 lines 12-29), and that at step 504 the CPU 200 adjusts its programming parameters accordingly (White, column 8 lines 30-45), so that the items and steps are determined corresponding to each product.
in accordance with the burning items and the burning steps, burning the multiple pieces of burning data in parallel by means of the plurality of burning modules to the plurality of products to be burned (White, column 5 line 44 – column 6 line 24, column 6 lines 54-67, column 7 lines 13-35, column 4 lines 1-18, column 4 lines 25-39). White discloses that at step 314 the central controller 102 downloads the memorized sequence to each of the programming sites 100 (White, column 5 line 44 – column 6 line 24), that at step 318 the central controller enables each of the programming sites 100 for independent operation (White, column 6 lines 54-67), and that at step 406 the device is programmed according to the downloaded sequence of instructions and particular device characteristics (White, column 7 lines 13-35). The burning therefore proceeds in accordance with the determined burning items and burning steps. The parallelism of that burning is as set forth above with respect to claim 1 (White, column 4 lines 1-18, column 4 lines 25-39, column 7 lines 13-35).
Claims 2-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over White (US Pat. No. 6,351,774, hereinafter “White”) in view of Jin et al. (US Pub. No. 2009/0089469, hereinafter “Jin” – previously presented) and further in view of Li et al. (US Pub. No. 2007/0145993, hereinafter “Li” – previously presented).
With respect to claim 2 (Original), White in view of Jin is silent to disclose; however, in an analogous art, Li teaches the system further comprises a multi-channel control module (Li, Abstract; ¶[0006], ¶[0010], ¶[0012], ¶[0013]; FIG. 1). Li discloses a chip burning system that includes, in addition to the burning device 10 that supplies the burning data and the chips 40, 50 that receive it, a control unit 20 and a transforming circuit 30 (Li, ¶[0010]). The control unit 20 is used to control the burning process and includes a plurality of control terminals 25, 26, 27, and 28, the terminal 28 outputting a chip choosing signal for choosing a chip (Li, ¶[0012]). The transforming circuit 30 is connected to the control unit 20 through parallel input and output ports 32, 34 and is connected to the chips through two series of terminals (Li, ¶[0013]). The control unit 20 together with the transforming circuit 30 governs plural burning channels and is therefore the recited multi-channel control module.
the multi-channel control module is connected between the plurality of slave host computers and the plurality of burning modules (Li, ¶[0010], ¶[0011], ¶[0013]; FIG. 1). Li discloses that the control unit 20 and the transforming circuit 30 are interposed in the signal path between the burning device 10, which is the source of the burning data, and the chips 40, 50 that are to receive it, with the burning device 10 connected to the control unit 20 and the transforming circuit 30 connected onward to the chips (Li, ¶[0010], ¶[0011], ¶[0013]). Li thus teaches placing the multi-channel control module at the intermediate position between the element that supplies the burning data and the elements that deliver it to the products, which is the recited position between the plurality of slave host computers and the plurality of burning modules when Li's teaching is incorporated into the architecture of White in view of Jin.
the multi-channel control module is configured to control the connection and disconnection of the plurality of burning channels (Li, ¶[0012], ¶[0016]–[0020], ¶[0026]–[0030]; FIG. 2). Li discloses that the transforming circuit 30 contains a plurality of buffers 303a–303k whose conducting state is governed by control signals from the control unit 20 (Li, ¶[0016]–[0020]). Li specifically discloses that the control terminals of the buffers 303d–303g and 303h–303k are connected to the terminal 28 of the control unit 20, so that when the chip choosing signal on terminal 28 is at a low level the buffers 303d–303g conduct and the path to the chip 40 is established while the path to the chip 50 is not, and when the chip choosing signal is at a high level the buffers 303h–303k conduct and the converse obtains (Li, ¶[0020], ¶[0026], ¶[0030]). Selectively establishing the signal path to one channel while breaking it to the other is the recited control of the connection and disconnection of the plurality of burning channels.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have modified the system of White in view of Jin by interposing the control unit and transforming circuit of Li between the CPUs 200 of the programming sites and the pin driver circuits 204, as taught by Li. One of ordinary skill would have been motivated to do so because White discloses that its programming sites are grouped together into a single unit called a programming station 104 (White, column 3 lines 27-37) and that the prior art suffered from the problem that multiple programmers integrated together may interfere with each other, a problem the art identifies as especially acute where devices of different types are present. Interposing Li's gated control unit and transforming circuit would allow each burning channel to be selectively activated under program control and would isolate the inactive channels so that they do not load or disturb the channel presently being programmed, which directly addresses that recognized interference problem and is the very purpose for which Li provides the chip choosing signal and the gated buffers (Li, ¶[0012], ¶[0020]). Doing so would additionally centralize the channel-selection logic in a single element rather than replicating it within each of White's programming sites, reducing the per-site hardware and software burden.
With respect to claim 3 (Original), Li further teaches the multi-channel control module comprises an adapter module (Li, ¶[0013], ¶[0014], ¶[0015], ¶[0028]; FIG. 1). Li discloses that the transforming circuit 30, which forms part of the multi-channel control module identified above with respect to claim 2, receives the burning data from the control unit 20 in parallel form through the parallel input and output ports 32, 34, and delivers it to the chips through the two series of terminals 351–354 and 361–364 in the form required by those chips (Li, ¶[0013]–[0015], ¶[0028]). A circuit that receives signals in the format used on the source side and converts them to the format required on the device side is an adapter module, and it is comprised within the multi-channel control module.
the multi-channel control module is configured to control the connection and disconnection in hardware of the plurality of burning modules to the adapter module, and/or to control the connection and disconnection in hardware of the plurality of slave host computers to the adapter module, so as to realize the connection and disconnection of the plurality of burning channels (Li, ¶[0016]–[0020], ¶[0026]–[0030]; FIG. 2). Li discloses that the control terminal of the buffer 303a is connected to the terminal 25 of the control unit 20, and that when the terminal 25 is enabled at a high level the buffer 303a conducts (Li, ¶[0019]). Li further discloses that the control terminals of the buffers 303d–303g and of the buffers 303h–303k are connected to the terminal 28 of the control unit 20, which determines which group of buffers conducts according to the level of the chip choosing signal, with the phase inverter 304b applied to one of the two groups so that exactly one group conducts at a time (Li, ¶[0020], ¶[0026], ¶[0030]). Gating the conducting state of buffers by a hardware control signal is control of connection and disconnection in hardware, and because those buffers lie in the path between the adapter module and the elements that deliver the burning data to the chips, that hardware gating realizes the connection and disconnection of the plurality of burning channels. Claim 3 further defines the multi-channel control module already credited to Li with respect to claim 2, and the motivation to combine set forth above with respect to claim 2 applies equally to claim 3.
With respect to claim 5 (Original), White in view of Li is silent to disclose the multi-channel control module is further configured to distribute power to the plurality of burning modules; however, in an analogous art, Jin teaches distributing power under the direction of the controlling element of a parallel burning system (Jin, ¶[0025], ¶[0026]). Jin discloses that the master micro controller unit 20 provides the power respectively to the burning chips according to their required voltage values (Jin, ¶[0025]), and that the master micro controller unit 20 is responsible for controlling and managing the power-on and power-off of all chips to be burned (Jin, ¶[0026]). Jin therefore teaches that the element which coordinates the plural burning channels is also the element that distributes and gates power within the system, rather than power being distributed independently of channel control.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have configured the multi-channel control module of White in view of Li to distribute power to the plurality of pin driver circuits, in the manner that Jin teaches for the controlling element of a parallel burning system. One of ordinary skill would have been motivated to do so because the multi-channel control module is, in the combination, the single element through which the burning-channel data and the channel-selection control signals for every channel already pass, so that consolidating power distribution into that same element reduces the number of separately controlled subsystems and allows power to be sequenced together with channel selection rather than by independent means. Such consolidation would further permit power to be gated on a per-channel basis, so that only the pin driver circuit on the currently selected channel is energized, which serves the same channel-isolation objective that motivates Li's gated buffers (Li, ¶[0020]) and which corresponds directly to the power-on and power-off control that Jin assigns to the system controller (Jin, ¶[0026]). Energizing only the active channel would additionally reduce the risk that a channel in an unpowered or fault state disturbs the channel being programmed.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over White (US Pat. No. 6,351,774, hereinafter “White”) in view of Jin et al. (US Pub. No. 2009/0089469, hereinafter “Jin” – previously presented) in view of Li et al. (US Pub. No. 2007/0145993, hereinafter “Li” – previously presented) and further in view of Knauer (US Pat. No. 5,644,115, hereinafter “Knauer”).
With respect to claim 4 (Original), White teaches the number of the slave host computers, and the number of the burning modules are the same (White, Abstract; column 2 lines 39-54; column 3 lines 57-67, column 4 line 40 – column 5 line 11). White discloses that each programming site 100 includes identical logic and features (White, column 3 lines 57-67), and that within a programming site 100 a central processing unit (CPU) 200 couples to memory 202 and to a pin driver circuit 204 (White, column 4 lines 40-63), the pin drivers 204 being coupled to the receptacle 205 that holds the device (White, column 4 line 64 – column 5 line 11). Because every site contains exactly one CPU 200 and exactly one pin driver circuit 204, and every site is identical, the number of CPUs across the system equals the number of pin driver circuits across the system. The number of the slave host computers and the number of the burning modules are therefore the same.
White in view of Jin and further in view of Li is silent to disclose; however, in an analogous art, Knauer teaches the adapter module comprises a first group of adapters and a second group of adapters (Knauer, Abstract; column 1 line 56 – column 2 line 12, column 2 lines 37-64; column 3 line 57 – column 4 line 15, column 5 lines 9-21, column 5 lines 23-44). Knauer discloses a switching matrix 10 comprising a mother board 12 and a relay board 14, on which an input panel 22 is mounted having installed thereon a plurality of input connectors 24, and on which a separate pathway panel 26 is mounted having installed thereon a plurality of pathway connectors 28 (Knauer, column 3 line 57 – column 4 line 15). Knauer thereby discloses a single board-level adapter assembly carrying two distinct and separately panelled groups of connectors. Knauer further discloses that the two groups are carried on opposite sides of the board, teaching that the input conductors are disposed on one side of the board and the pathway conductors are disposed on an opposite side of the board (Knauer, column 2 lines 1-12), that the input conductors are disposed in columns defining a first plane while the pathway conductors are disposed in rows defining a second plane (Knauer, column 2 lines 1-12), and that the input guard tubes and bars are installed on the front face 27 of the relay board 14 while the pathway guard tubes 70 are installed on the rear face 72 of the relay board 14 (Knauer, column 5 lines 15-36). Each connector adapts the signals carried on the board conductors to the mating external lead connector, the input connectors 60 mating with test lead connectors 99 and the pathway connectors 28 mating with pathway lead connectors 103 (Knauer, column 5 lines 10-15), column 5 lines 36-44); each is therefore an adapter, and the two panelled sets are the recited first and second groups of adapters.
the first group of adapters are connected to the plurality of slave host computers (Knauer, column 2 lines 37-42; column 5 lines 37-44, column 5 line 66 – column 6 line 21; claim 15). Knauer discloses that a plurality of pathway connectors are each connected to a corresponding one of the second conductors and are adapted to be connected to a test apparatus (Knauer, column 2 lines 37-42; claim 15), and that one or more test instruments 100 are connected to the pathway connectors 28 by pathway leads 102 and mating connectors 103 (Knauer, column 5 line 66 – column 6 line 21). The pathway connector group is thus the group facing the instrumentation that originates and receives the signals, which in the combination is the side occupied by the programming site CPUs of White; that group is connected one connector to one corresponding conductor, i.e., one adapter per channel.
the second group of adapters are connected to the plurality of burning modules (Knauer, column 2 lines 37-42; column 5 lines 10-15, column 5 line 66 – column 6 line 21; claim 15). Knauer discloses that a plurality of input connectors are each connected to a corresponding one of the first conductors and are adapted to be connected to a device under test (Knauer, column 2 lines 37-42; claim 15), that each input connector 60 is adapted to mate with a test lead connector 99 from a test lead connectable to a device under test 96 (Knauer, column 5 lines 10-15), and that circuits of a device under test 96 are connected to the input connectors 24 with suitable test leads 98 and mating connectors 99 (Knauer, column 5 line 66 – column 6 line 21). The input connector group is thus the group facing the hardware at the device end of each channel, which in the combination is the side occupied by the pin driver circuits of White. Knauer further discloses that the switching elements are interposed between the two groups, teaching that the relays are disposed between the input circuits and the pathway circuits (Knauer, column 5 line 66 – column 6 line 21; claim 16) and that the switches are disposed between the first and second planes occupied respectively by the two conductor sets (Knauer, column 2 lines 1-12), so that the two adapter groups face opposite ends of the channel and the gating elements lie between them.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have constructed the adapter module of White in view of Jin and further in view of Li as a board carrying a first group of adapters on one face directed to the programming site processors and a second group of adapters on the opposite face directed to the pin driver circuits, with the gating elements disposed between the two groups, as taught by Knauer. One of ordinary skill would have been motivated to do so because Knauer teaches that disposing the two conductor groups in separate parallel planes on opposite faces of the board with the switching elements between them minimizes the circuit lengths and the insulation required, thereby reducing losses as well as noise, interference, and other problems (Knauer, column 1 lines 42-53), and that the resulting arrangement reduces dielectric absorption and triboelectric effects and shortens the duration of transient states, permitting increased switching rates (Knauer, column 3 lines 18-22). Those benefits apply directly to the combination, in which each burning channel must be gated on and off while the signal integrity of the channel presently burning is preserved, and in which higher switching rates translate into higher production throughput of the kind White seeks (White, column 4 lines 25-39).
White in view of Jin in view of Knauer is further silent to disclose that; however, in an analogous art, Li teaches:
the number of adapters in the first group of adapters, the number of adapters in the second group of adapters are the same (Li, ¶[0016], ¶[0017], ¶[0020]; FIG. 2), as set forth above with respect to claim 3, Li disclosing a first group of four buffers 303d, 303e, 303f, and 303g and a second group of four buffers 303h, 303i, 303j, and 303k, each group gated in unison and equal in number to the other (Li, ¶[0020]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have provided the first group of adapters and the second group of adapters of the combination with the same number of adapters, as taught by Li. One of ordinary skill would have been motivated to do so because Li teaches gating its two adapter groups in unison and in complementary fashion, so that exactly one group conducts at any time (Li, ¶[0020], ¶[0026], ¶[0030]), an arrangement that presupposes a matching adapter in each group for every channel to be routed; an unequal arrangement would leave one or more channels without a counterpart adapter on one side and therefore incapable of being routed or gated. One of ordinary skill would further have been motivated because the number of channels in the combination is fixed by the number of programming sites, each contributing exactly one processor and exactly one pin driver circuit (White, column 3 lines 57-67, column 4 lines 40-63), so that sizing each adapter group to that channel count leaves neither a channel unrouted nor an adapter unused, and because Knauer likewise connects each connector of a group to a corresponding one of the conductors of that group, that is, one adapter per channel (Knauer, column 2 lines 38-43; claim 15).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over White (US Pat. No. 6,351,774, hereinafter “White”) in view of Jin et al. (US Pub. No. 2009/0089469, hereinafter “Jin” – previously presented) and further in view of Liu Bin et al. (CN109086055, hereinafter “Bin” – previously presented).
With respect to claim 6 (Original), White in view of Jin is silent to disclose; however, in an analogous art, Bin teaches the system further comprises a verification module (Bin, Abstract; ¶[0018], ¶[0042]). Bin discloses a multi-channel offline programmer in which a data verification module 5-4 is provided as a discrete constituent module of the programming apparatus alongside the modules that transfer the programming data (Bin, ¶[0018], ¶[0042]).
the verification module is configured to perform data verification on the plurality of products to be burned during the processing of the plurality of products to be burned (Bin, ¶[0018], ¶[0042]). Bin discloses that the data verification module 5-4 verifies the programming data of each channel as part of the programming operation, so that the verification is performed on the devices being programmed while the programming operation is under way rather than as a separate later stage (Bin, ¶[0018], ¶[0042]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have modified the system of White in view of Jin to include the data verification module taught by Bin. One of ordinary skill would have been motivated to do so because White already recognizes the need to confirm that code has been correctly transferred into the device, teaching that the programming sites include status detection circuitry to detect the status of transfer of the code into the device, that after the transfer cycle is complete the status detector senses and causes an indicator to indicate whether a particular device has satisfactorily completed receipt of the code or whether the code transfer was faulty (White, column 2 lines 55-67), and that the selectable options include blank checking and verification after programming (White, column 5 lines 26-45). Implementing that recognized verification need as a discrete verification module of the kind Bin provides for a comparable multi-channel programmer would consolidate the verification logic for all channels in one module rather than replicating it at every site, and would permit detection of data-integrity faults arising during transmission across the parallel burning channels, which is of particular value in a parallel system where a single upstream fault may otherwise be replicated across many channels at once.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over White (US Pat. No. 6,351,774, hereinafter “White”) in view of Jin et al. (US Pub. No. 2009/0089469, hereinafter “Jin” – previously presented) in view of Chen Sibo et al. (CN107992317, hereinafter “Sibo” – previously presented) and further in view of Haase (US Pub. No. 2017/0293484, hereinafter “Haase” – previously presented).
With respect to claim 9 (Currently Amended), White in view of Jin is silent to disclose; however, in an analogous art, Sibo teaches each product to be burned is a battery management unit (BMU) of a pack (Sibo, Abstract; ¶[0015], ¶[0016], ¶[0017]). Sibo discloses programming battery cell power management and current monitoring integrated circuits, that is, the management electronics associated with the individual cells of a battery assembly, and discloses doing so by multi-channel parallel writing in a production context (Sibo, ¶[0015]–[0017]). The battery cell management integrated circuit of a battery assembly is a battery management unit of a pack.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have applied the concurrent programming system of White in view of Jin to the battery management units taught by Sibo. One of ordinary skill would have been motivated to do so because White expressly teaches that each programming site is capable of programming a variety of programmable devices including programmable microcontrollers and other devices containing a programmable element (White, column 3 lines 57-67), so that a battery management unit is within the class of devices White's system is designed to program, and because Sibo teaches that such units are in fact programmed by multi-channel parallel writing in production (Sibo, ¶[0015]–[0017]), for which White's independently operating multi-site architecture and its attendant throughput advantage (White, column 4 lines 25-39) would be directly applicable. This is the simple substitution of one known programmable target for another to obtain predictable results.
White in view of Jin, and further in view of Sibo, is silent to disclose; however, in an analogous art, Haase teaches burning data corresponding to each BMU contains an underlying jump file and application software (Haase, ¶[0030], ¶[0031], ¶[0038]). Haase discloses a microcontroller having a first firmware component arranged in a first memory area and a second firmware component arranged in a second memory area, and gives as an example a partition of approximately 4 kB for the one component and 59 kB for the other (Haase, ¶[0030]). Haase discloses that the second firmware component is a bootloader configured to exchange the first, application firmware component (Haase, ¶[0031]), and that the first firmware component is the application while the second firmware component is the bootloader (Haase, ¶[0038]). The bootloader is the low-level resident component that executes on start-up and transfers execution to the application component; it is therefore an underlying jump file within the broadest reasonable interpretation of that term, and the application component is the recited application software. The programming payload written to the device accordingly contains both components.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have modified the burning data of White in view of Jin and further in view of Sibo so that the data written to each battery management unit contains a bootloader component and an application component, as taught by Haase. One of ordinary skill would have been motivated to do so because a resident bootloader permits the application firmware of a deployed unit to be replaced in the field without returning the unit to the factory (Haase, ¶[0031]), which is of evident value for battery management units that are installed inside assembled packs and are not readily accessible after assembly, and because writing both components in a single factory operation takes advantage of the parallel throughput of White's multi-site architecture (White, column 4 lines 25-39) rather than requiring a second programming pass for the application component.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over White (US Pat. No. 6,351,774, hereinafter “White”) in view of Jin et al. (US Pub. No. 2009/0089469, hereinafter “Jin” – previously presented) and further in view of Song (US Pub. No. 2015/0144690, hereinafter “Song” – previously presented).
With respect to claim 11 (Original), the limitation the system further comprises a burning file management system is taught by Jin for the reasons set forth above with respect to claim 7 (Jin, ¶[0026], ¶[0030]; FIG. 1), namely, the computer 10 which is separate from the master micro controller unit 20 and which holds the per-chip chip type, bus type, and program data.
White in view of Jin is silent to disclose; however, in an analogous art, Song teaches scanning graphic identifiers on the plurality of products to be burned to obtain the product numbers of the plurality of products to be burned (Song, Abstract; ¶[0007], ¶[0008]; claim 1). Song discloses a detection system suitably used on a production line comprising a plurality of detection printed circuit boards, each having a bar code, a conveying belt carrying the boards, and a bar code reading device arranged on the belt and reading a production serial number corresponding to the bar code (Song, Abstract; claim 1). The bar code borne on each board is a graphic identifier on a product, and reading it to obtain that board's production serial number is the recited scanning to obtain the product number.
obtaining, based on the product numbers of the plurality of products to be burned, multiple pieces of burning data corresponding to the plurality of products to be burned from the burning file management system (Song, Abstract; ¶[0008], ¶[0009]; claim 1). Song discloses a detection drafting library storing the production serial number and a corresponding detection drafting, so that the per-product processing data applicable to a given board is retrieved from the stored library using that board's scanned production serial number as the index (Song, Abstract; claim 1). Song thereby teaches obtaining, on the basis of the scanned product number, the per-product data corresponding to that product from a stored file repository.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have modified the method of White in view of Jin so that the product numbers are obtained by scanning graphic identifiers borne on the products, and so that the corresponding burning data is retrieved from the burning file management system on the basis of the scanned product numbers, as taught by Song. One of ordinary skill would have been motivated to do so because White identifies operator error in identifying and tracking devices at the sites as a recognized problem, teaching that if a machine operator was distracted or interrupted when loading or unloading an array of programming sites it was very difficult to determine whether the devices were beginning blank ones or completed programmed devices (White, column 1 line 57 – column 2 line 15), and because automating identifier capture by bar code reading, as Song teaches, removes the manual-entry path by which a product may be bound to the wrong burning data record. Automated scanning would further permit the workflow to scale to high-volume production in which many products are programmed in parallel and each must be paired with its own correct per-product data, which is the operating condition of White's multi-site system (White, column 4 lines 25-39).
Claims 12-13, 15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over White (US Pat. No. 6,351,774, hereinafter “White”) in view of Jin et al. (US Pub. No. 2009/0089469, hereinafter “Jin” – previously presented) in view of Song (US Pub. No. 2015/0144690, hereinafter “Song” – previously presented) and further in view of Hawig et al. (US Pub. No. 2004/0148073, hereinafter “Hawig” – previously presented).
With respect to claim 12 (Original), White in view of Jin and further in view of Song is silent to disclose; however, in an analogous art, Hawig teaches determining first data identifiers of the multiple pieces of burning data obtained from the burning file management system (Hawig, ¶[0052], ¶[0053], ¶[0054], ¶[0055], ¶[0071], ¶[0072]). Hawig discloses that the programming data set transmitted to the unit being programmed carries, in addition to the memory-map contents to be written, identifier fields including a software version identifier and a software number identifier (Hawig, ¶[0071], ¶[0072]), and that these identifier fields are read from the description data record accompanying the programming data before the programming operation begins (Hawig, ¶[0052]–[0055]). Reading those identifier fields from the retrieved burning data record is the recited determining of first data identifiers.
determining a pre-stored first corresponding relationship between products to be burned and burning data (Hawig, ¶[0052], ¶[0053], ¶[0054], ¶[0055], ¶[0070], ¶[0074]). Hawig discloses a description data record that stores, for each authorized hardware product number, the programming data authorized for that hardware (Hawig, ¶[0052]–[0055], ¶[0070]), and further discloses that a single programming data file may contain different memory-maps for different hardware product numbers, so that the record expressly associates particular products with the particular burning data belonging to them (Hawig, ¶[0074]). Accessing that stored association prior to programming is the recited determining of a pre-stored first corresponding relationship.
performing a first verification on the multiple pieces of burning data on the basis of the first corresponding relationship and the first data identifiers of the multiple pieces of burning data (Hawig, ¶[0022], ¶[0065], ¶[0066], ¶[0070]). Hawig discloses that the programming data set contains an equipment description of the control units authorized for programming so that the control unit can perform an identity check before the operating program is started (Hawig, ¶[0022]), and that the unit compares the identifiers carried by the programming data set against the authorized range recorded in that description before permitting the operation (Hawig, ¶[0065], ¶[0066], ¶[0070]). That comparison of the data identifiers against the stored correspondence is the recited first verification.
in the case of a first verification result indicating a successful verification, calling the plurality of slave host computers to transmit the multiple pieces of burning data to the plurality of burning modules via the plurality of burning channels (Hawig, ¶[0022], ¶[0024], ¶[0065], ¶[0066]). Hawig discloses that the identity check is performed before the operating program is started and that the programming operation proceeds only where that check is satisfied, the operation being gated on the outcome (Hawig, ¶[0022], ¶[0024], ¶[0065], ¶[0066]). Conditioning the downloading and enabling steps of White upon a successful outcome of that check is the recited conditional calling.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have modified the method of White in view of Jin and further in view of Song to perform the pre-programming identity check taught by Hawig before transmitting the burning data to the programming sites. One of ordinary skill would have been motivated to do so because White's method already conditions progression on verification outcomes at other stages, teaching that if the operation fails the central controller 102 aborts further operations until the operator can determine the cause of the error and that if the operation passes the central controller proceeds (White, column 6 lines 31-41), so that a check gating the download step is consistent with the control flow White already employs. Performing the check before rather than after the data is written would prevent the wrong firmware version from being committed to a product that has been scanned and identified, and would block a mismatched product-and-data pair before any device is altered, which is of heightened value in White's parallel architecture where a single misconfigured download is distributed to many sites at once and would otherwise be replicated across every channel (White, column 5 lines 26-45, column 6 lines 54-67).
With respect to claim 13 (Currently Amended), White in view of Jin and further in view of Song is silent to disclose; however, in an analogous art, Hawig teaches determining, based on the product number of each product to be burned, a second data identifier of each product to be burned from the first corresponding relationship (Hawig, ¶[0052], ¶[0053], ¶[0054], ¶[0055], ¶[0070], ¶[0074]). Hawig discloses that the identity check proceeds from the hardware product number of the unit to be programmed, which is used to locate that unit's entry in the description data record, and that the authorized software version and software number for that hardware are read from the located entry (Hawig, ¶[0052]–[0055], ¶[0070], ¶[0074]). The authorized identifier so retrieved is the recited second data identifier, and it is determined from the first corresponding relationship on the basis of the product number, the product number itself being obtained by the scanning step of claim 11 (Song, Abstract; claim 1).
determining a first verification result that indicates a successful verification when the first data identifier of each product to be burned matches the second data identifier of the product to be burned (Hawig, ¶[0022], ¶[0024], ¶[0065], ¶[0066]). Hawig discloses that where the identifier carried by the programming data set corresponds to the authorized identifier read from the description data record, the identity check is satisfied and the programming operation is permitted to proceed (Hawig, ¶[0022], ¶[0024], ¶[0065], ¶[0066]). A satisfied identity check is a verification result indicating a successful verification.
determining a first verification result that indicates a failed verification when the first data identifier of each product to be burned does not match the second data identifier of the product to be burned (Hawig, ¶[0022], ¶[0065], ¶[0066], ¶[0070]). Hawig discloses that where the identifier carried by the programming data set falls outside the authorized range recorded in the description data record, the identity check is not satisfied and the programming operation is not permitted (Hawig, ¶[0022], ¶[0065], ¶[0066], ¶[0070]). An unsatisfied identity check is a verification result indicating a failed verification. Claim 13 further defines the first verification already credited to Hawig with respect to claim 12, and the motivation to combine set forth above with respect to claim 12 applies equally to claim 13.
With respect to claim 15 (Currently Amended), White in view of Jin and further in view of Song is silent to disclose; however, in an analogous art Hawig teaches performing a second verification on the plurality of burned products before assembling the plurality of burned products (Hawig, ¶[0022], ¶[0065], ¶[0066], ¶[0070], ¶[0071], ¶[0072], ¶[0074]). Hawig discloses an identity check in which the identifiers borne by a programmed unit, including its hardware product number, its serial number, and its software version, are compared against the authorized entries of a stored description data record, and discloses that the check may be conditioned on a serial number restriction and on a software version restriction (Hawig, ¶[0070]–[0072], ¶[0074]). Hawig thereby teaches a verification, distinct from and subsequent to the pre-programming check of claim 12, that is applied to a unit whose firmware has already been written and that confirms the unit carries the firmware authorized for it before the unit is permitted to progress.
in the case of a second verification result indicating a successful verification, assembling the plurality of burned products to obtain a plurality of packs (Hawig, ¶[0022], ¶[0024]). Hawig discloses that the succeeding operation is permitted only upon a satisfied identity check, the progression from one stage to the next being gated on the verification outcome (Hawig, ¶[0022], ¶[0024]). Gating the succeeding assembly operation on a satisfied check is the recited conditional assembling. That the articles assembled are packs follows from the battery management unit product context of claim 9 (Sibo, ¶[0015]–[0017]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have modified the method of White in view of Jin and further in view of Song to perform the identity check taught by Hawig on the programmed products before those products are assembled. One of ordinary skill would have been motivated to do so because White already teaches verifying each device after its programming cycle and reporting the result before the device is released from the site (White, column 2 lines 55-67; column 7 lines 36-48, column 8 lines 1-11), so that a verification checkpoint standing between programming and the next production operation is consistent with White's own workflow. Placing that checkpoint before assembly would prevent a product bearing the wrong firmware, or a product from the wrong production batch, from being built into a pack from which its later removal would require disassembly, and would catch mis-programming arising during the parallel burning step at the point where the cost of correction is lowest, the value of the workpiece rising as it advances along the line.
With respect to claim 18 (Original), and applying the interpretation of the products to be burned in the plurality of packs set forth in the rejection under 35 U.S.C. 112(b) above White in view of Jin and further in view of Song is silent to disclose; however, in an analogous art Hawig teaches determining a pre-stored first corresponding relationship between products to be burned and burning data (Hawig, ¶[0052], ¶[0053], ¶[0054], ¶[0055], ¶[0070], ¶[0074]), for the reasons set forth above with respect to the corresponding limitation of claim 12, namely the description data record associating each authorized hardware product number with the programming data authorized for it, including the disclosure that one programming data file may hold different memory-maps for different hardware product numbers (Hawig, ¶[0074]).
performing a third verification on the products to be burned in the plurality of packs on the basis of data identifiers of the burning data corresponding to the products to be burned in the plurality of packs and the first corresponding relationship (Hawig, ¶[0022], ¶[0052]–[0055], ¶[0065], ¶[0066], ¶[0070], ¶[0074]). Hawig discloses that the identity check compares the data identifiers borne by the burning data of a unit against the authorized identifiers indexed to that unit's hardware product number in the stored description data record (Hawig, ¶[0022], ¶[0065], ¶[0066], ¶[0070]), and Hawig imposes no limit on the number of occasions on which that check may be applied. Applying that same comparison to the programmed products now contained within the assembled packs is a further, third application of Hawig's identity check, performed on the basis of the data identifiers of the burning data and the pre-stored first corresponding relationship.
in the case of a third verification result indicating a successful verification, performing a performance test on the plurality of packs (Hawig, ¶[0022], ¶[0024]). Hawig discloses the gated progression by which the succeeding operation is permitted only upon a satisfied identity check (Hawig, ¶[0022], ¶[0024]). Conditioning a performance test of the assembled packs on a satisfied third check applies that gated progression to the performance-test operation.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have modified the method of White in view of Jin and further in view of Song to perform a further identity check of the kind taught by Hawig on the products contained in the assembled packs, and to condition the performance testing of those packs on that check. One of ordinary skill would have been motivated to do so in order to detect units that were swapped, mis-routed, or otherwise disassociated from their programming record during the intervening assembly operations, a possibility that the earlier pre-assembly check cannot exclude because it occurs before those operations take place, and in order to avoid expending performance-test capacity on packs already known to contain mis-programmed units. Hawig itself teaches applying the identity check at the point immediately preceding the operation to be protected (Hawig, ¶[0022], ¶[0024]), and the performance test of the assembled pack is such an operation.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over White (US Pat. No. 6,351,774, hereinafter “White”) in view of Jin et al. (US Pub. No. 2009/0089469, hereinafter “Jin” – previously presented) in view of Song (US Pub. No. 2015/0144690, hereinafter “Song” – previously presented) in view of Hawig et al. (US Pub. No. 2004/0148073, hereinafter “Hawig” – previously presented) and further in view of Chen Sibo et al. (CN107992317, hereinafter “Sibo” – previously presented).
With respect to claim 16 (Original), the combination of White in view of Jin, further in view of Song, and further in view of Hawig is silent to disclose; however, in an analogous art, Sibo teaches obtaining a second corresponding relationship between products to be burned and packs that is stored during burning (Sibo, Abstract; ¶[0015], ¶[0016], ¶[0017], ¶[0019]). Sibo discloses a multi-channel parallel writing operation for battery cell management integrated circuits in which the record written in association with each product at the time of programming carries per-product identifying information, expressly including the serial number assigned to that product and the panel position occupied by that product, together with the programming information for that product (Sibo, ¶[0016]). Sibo further discloses encoding those per-product assignments as part of the parallel writing operation itself (Sibo, ¶[0017], ¶[0019]), so that the assignment record is created and stored during burning rather than afterward. Recording in that same per-product register the assembly to which each product is allocated yields a stored correspondence between the products and the packs, and reading that register back at the verification station is the recited obtaining of the second corresponding relationship.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have modified the method of White in view of Jin, further in view of Song, and further in view of Hawig to create and store during burning a record binding each product to its pack, as taught by Sibo. One of ordinary skill would have been motivated to do so because Sibo already creates a per-product register at the time of programming that carries the product's serial number and its physical position (Sibo, ¶[0016]), so that carrying the pack allocation in that same register requires no additional data structure and no additional write operation, and because a record created at the moment of burning captures the allocation while the product is still individually identified at its programming channel, which is the last point in the flow at which the binding can be recorded without re-identifying the product.
The combination of White in view of Jin, further in view of Hawig, and further in view of Sibo is silent to disclose; however, in an analogous art, Song teaches:
Song teaches scanning graphic identifiers of the plurality of burned products to obtain product numbers of the plurality of burned products, and battery identifiers of the packs respectively corresponding to the plurality of burned products (Song, Abstract; ¶[0007], ¶[0008], ¶[0009]; claim 1). Song discloses a detection system used on a production line comprising a plurality of printed circuit boards each bearing a bar code, a conveying belt transporting those boards, and a bar code reading device arranged on the belt that reads the production serial number corresponding to the bar code of each board as it passes (Song, Abstract; claim 1). Song thereby teaches acquiring an article's identifying number by optically reading a graphic identifier borne on that article at a station on the line. Applying that same reading operation at the assembly station to the graphic identifiers borne on the burned products and to those borne on the packs yields, respectively, the recited product numbers of the burned products and the battery identifiers of the packs corresponding to them.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have modified the method of White in view of Jin, further in view of Hawig, and further in view of Sibo to acquire the product numbers and the pack battery identifiers by scanning graphic identifiers at the assembly station, as taught by Song. One of ordinary skill would have been motivated to do so because the stored product-to-pack record is of no use unless the corresponding identifiers are captured at the point where the products and packs are brought together, and because manual capture at that point is precisely the error path White identifies when it teaches that an operator who is distracted or interrupted while loading or unloading finds it very difficult to determine which devices are which (White, column 1 line 57 – column 2 line 15). Song's bar code reading device removes that manual step and captures both identifiers automatically as the articles pass the station (Song, Abstract; claim 1).
The combination of White in view of Jin, further in view of Sibo, and further in view of Song is silent to disclose; however, in an analogous art, Hawig teaches performing a second verification on the plurality of burned products on the basis of the product numbers of the plurality of burned products, the battery identifiers respectively corresponding to the plurality of burned products, and the second corresponding relationship (Hawig, ¶[0022], ¶[0052], ¶[0053], ¶[0054], ¶[0055], ¶[0065], ¶[0066], ¶[0070]). Hawig discloses an identity check in which identifiers acquired from the article under examination are compared against the authorized entries held in a stored description data record, the check being performed before the article is permitted to proceed (Hawig, ¶[0022], ¶[0065], ¶[0066]). Hawig discloses that the stored record associates particular articles with the particular data belonging to them, indexed by the article's own identifying number (Hawig, ¶[0052]–[0055], ¶[0070]). Applying that compare-acquired-identifiers-against-the-stored-record mechanism to the product numbers and battery identifiers acquired at the assembly station, checked against the product-to-pack record stored during burning, is the recited performing of the second verification on the basis of those three inputs.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have modified the method of White in view of Jin, further in view of Sibo, and further in view of Song to perform the second verification by comparing the acquired identifiers against the stored product-to-pack record in the manner Hawig teaches for its identity check. One of ordinary skill would have been motivated to do so because acquiring the product numbers and battery identifiers accomplishes nothing unless they are tested against the allocation recorded during burning, and Hawig supplies the established mechanism for exactly that test, comparing acquired identifiers against a stored authorization record and returning an outcome on which further progression depends (Hawig, ¶[0022], ¶[0024], ¶[0065], ¶[0066]). Applying that mechanism here confirms that each burned product has in fact been placed in the pack to which it was allocated, and preserves traceability between the programming record and the finished assembly.
With respect to claim 17 (Original), The combination of White in view of Jin, further in view of Sibo, and further in view of Song is silent to disclose; however, in an analogous art, Hawig further teaches determining a second verification result that indicates a successful verification when the product numbers of the plurality of burned products and the battery identifiers respectively corresponding to the plurality of burned products match the second corresponding relationship (Hawig, ¶[0022], ¶[0024], ¶[0065], ¶[0066]). Hawig discloses that where the identifiers acquired from the article correspond to the authorized entries held in the stored correspondence record, the identity check is satisfied and the succeeding operation is permitted (Hawig, ¶[0022], ¶[0024], ¶[0065], ¶[0066]). Applied to the acquired product numbers and battery identifiers compared against the second corresponding relationship, a correspondence yields a verification result indicating a successful verification.
determining a second verification result that indicates a failed verification when the product numbers of the plurality of burned products and the battery identifiers respectively corresponding to the plurality of burned products do not match the second corresponding relationship (Hawig, ¶[0022], ¶[0065], ¶[0066], ¶[0070]). Hawig discloses that where the acquired identifiers fall outside the authorized entries of the stored record, the identity check is not satisfied and the succeeding operation is not permitted (Hawig, ¶[0022], ¶[0065], ¶[0066], ¶[0070]). Applied to the same comparison, a non-correspondence yields a verification result indicating a failed verification.
Claim 17 further defines the second verification already credited to Hawig with respect to claim 16, and the motivation to combine set forth above with respect to claim 16 applies equally to claim 17.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over White (US Pat. No. 6,351,774, hereinafter “White”) in view of Jin et al. (US Pub. No. 2009/0089469, hereinafter “Jin” – previously presented) in view of Liu Bin et al. (CN109086055, hereinafter “Bin” – previously presented) and further in view of Hawig et al. (US Pub. No. 2004/0148073, hereinafter “Hawig” – previously presented).
With respect to claim 19 (Original), and noting that claim 19 depends directly from claim 10 and therefore does not incorporate the first, second, and third verifications as those terms are defined in claims 12, 15, and 18, which are not parents of claim 19, the recitation the data verification comprising a first verification, a second verification, and a third verification is given its broadest reasonable interpretation as requiring that the recited data verification comprise three distinct verification operations.
White in view of Jin is silent to disclose; however, in an analogous art, Bin teaches the system further comprises a verification module (Bin, Abstract; ¶[0018], ¶[0042]), for the reasons set forth above with respect to claim 6, namely the data verification module 5-4 provided as a discrete constituent module of the multi-channel offline programmer (Bin, ¶[0018], ¶[0042]).
performing, by the verification module, data verification on the plurality of products to be burned during the processing of the plurality of products to be burned (Bin, ¶[0018], ¶[0042]). Bin discloses that the data verification module 5-4 verifies the programming data of each channel as part of the programming operation itself, so that the verification is carried out on the devices being programmed while the processing of those devices is under way (Bin, ¶[0018], ¶[0042]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have modified the system and method of White in view of Jin to include the data verification module taught by Bin and to perform the data verification by that module during processing, for the reasons set forth above with respect to claim 6, namely that White already recognizes the need to confirm correct transfer of code into the device (White, column 2 lines 55-67; column 5 lines 26-45) and that consolidating that verification in a single module serving all channels avoids replicating the logic at every site and permits detection of data-integrity faults arising across the parallel burning channels.
White in view of Jin, and further in view of Bin, is silent to disclose; however, in an analogous art, Hawig teaches the data verification comprising a first verification, a second verification, and a third verification (Hawig, ¶[0022], ¶[0052]–[0055], ¶[0065], ¶[0066], ¶[0070], ¶[0071], ¶[0072], ¶[0074]). Hawig discloses that the identity check performed before programming is composed of plural distinct verification operations, each directed to a different identifier class and each independently capable of blocking the operation: a check against the hardware product number recorded in the description data record (Hawig, ¶[0052]–[0055], ¶[0070], ¶[0074]), a check against a serial number restriction (Hawig, ¶[0070]), and a check against a software version restriction (Hawig, ¶[0071], ¶[0072]). Hawig thereby teaches a data verification comprising three distinct verification operations performed on the article being programmed.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have modified the verification module of White in view of Jin and further in view of Bin so that the data verification it performs comprises three distinct verification operations, as taught by Hawig. One of ordinary skill would have been motivated to do so because a single check directed to one identifier class cannot detect faults of the other classes, and Hawig identifies each of the hardware identity, the serial number, and the software version as an independent ground on which programming must be blocked (Hawig, ¶[0070]–[0072], ¶[0074]). Providing all three checks within the single verification module of Bin would allow each independent fault class to be caught by the same module during processing without requiring separate inspection stages, which is consistent with White's objective of maintaining production throughput at the programming stations (White, column 4 lines 25-39).
Alternate Claim Rejections - 35 USC § 103
Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over White (US Pat. No. 6,351,774, hereinafter “White”) in view of Jin et al. (US Pub. No. 2009/0089469, hereinafter “Jin” – previously presented) and further in view of Carson et al. (US Pub. No. 2009/0138841, hereinafter “Carson”).
This ground is presented in the alternative, and applies only to the limitation each of the plurality of burning modules comprises physical circuitry to perform burning operations of claim 1 and the limitation wherein the plurality of burning modules perform burning operations of claim 10. Every other limitation of claims 1 and 10 is mapped as set forth above in the rejection over White in view of Jin, and those mappings are relied upon here. This ground is presented to address the contention, should Applicant advance it, that a pin driver circuit operating under the direction of a site processor is not itself an element that performs burning operations.
With respect to claims 1 and 10, White in view of Jin is silent to disclose, on that contention only, each of the plurality of burning modules comprises physical circuitry to perform burning operations; however, in an analogous art, Carson teaches each of the plurality of burning modules comprises physical circuitry to perform burning operations (Carson, ¶[0032], ¶[0076], ¶[0080], ¶[0081], ¶[0082], ¶[0083]). Carson discloses a system for the programming of programmable devices attached to circuit boards in which processing of information is carried out at three processing levels: at a first processing level is a host computer programmed to load digital information into a subsidiary processor; at a second processing level is a subsidiary processor programmed to execute a device algorithm; and at a third processing level is an FPGA programmed to execute a bus algorithm (Carson, ¶[0032], ¶[0081]). As to the third level, Carson states that during the programming phase the subsidiary processor 15 provides data for programming each device under test to the FPGA 16, and that the FPGA 16, using the bus algorithm 20, engages in the bus protocol for each of several devices under test and is the direct cause of writing each data element into each device under test (Carson, ¶[0080]). Carson further discloses that the bus algorithm is placed in the FPGA rather than being executed by a processor so that it handles communication to the devices at full hardware speed (Carson, ¶[0082]), while the subsidiary processor supplies the data elements and monitors the bus algorithm for completion of the previous cycle (Carson, ¶[0083]). Carson thereby teaches expressly that the element which performs the writing is a physical circuit distinct from, and operating under the direction of, the processor that supplies its data.
It would have been obvious to one of ordinary skill in the art at the time the invention was made before the effective filing date of the claimed invention to have implemented the device-facing programming hardware of each programming site of White in view of Jin as a dedicated protocol-executing circuit of the kind taught by Carson. One of ordinary skill would have been motivated to do so because Carson teaches that executing the device-facing bus protocol in hardware rather than by instruction-at-a-time execution in a processor allows the protocol to be carried out at full hardware speed (Carson, ¶[0082]), and because Carson teaches that leaving the data queue to be maintained upstream introduces delay in requesting and receiving the data over the external bus (Carson, ¶[0084]), both of which directly serve White's stated objective of increasing production throughput at the programming stations (White, column 4 lines 25-39). One of ordinary skill would further have been motivated by Carson's teaching that, because multiple different types of devices may be programmed, such a circuit may include multiple algorithms for interfacing with different types of devices and multiple different types of communication interfaces (Carson, ¶[0076]), which addresses the same mixed-device-type capability that White contemplates (White, column 3 line 57 – column 4 line 18) and that Jin's different bus types supply (Jin, ¶[0030]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANIBAL RIVERACRUZ/Primary Examiner, Art Unit 2192
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