DETAILED ACTION
This action is responsive to the following communication: the response filed 7/20/26. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-20 pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species II, Figs. 8 and 11, in the reply filed on 7/20/26 is acknowledged. The traversal is on the ground(s) that Figs. 8 and 11 encompass claims 1-3, 6-12, and 15-20. This is not found persuasive because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
For clarification purposes, claim 1 recites a first write transistor, configured to write a first input data to a first data storage node in response to a first write signal; a second write transistor, configured to write a second input data to a second data storage node in response to a second write signal. That is, claim 1 requires two different write signals which is not identical. However, claim 11 recites a second memory cell having an identical structure as, and immediately neighboring, the first memory cell; drawn to Figs. 8 and 11 having identical structures. Therefore, Figs. 8 and 11 does not appear to encompass claim 1-10.
Claim 18 recites a first memory cell comprising: a first write transistor; a first read transistor electrically coupled to the first write transistor; second memory cell comprising: a second write transistor; and a second read transistor electrically coupled to the second write transistor; a power supply node, wherein the power supply node is a VDD node or a VSS node; and a first dummy transistor. That is, claim 18 requires a dummy transistor only in one, i.e. the second memory cell, which is not identical. However, claim 11 recites a second memory cell having an identical structure as, and immediately neighboring, the first memory cell; and a first dummy transistor comprising at least a half in the first memory cell; drawn to Figs. 8 and 11 having identical structures and second memory cell having at least half the dummy transistor, identical to first memory cell. Therefore, Figs. 8 and 11 does not appear to encompass claim 18-20.
Further in light of the traversal, it is persuasive that claims 4-5 and 13-14 are not directed to Figs. 8 and 11, and are withdrawn. Therefore, as aforementioned, elected Species II drawn to Figs. 8 and 11, claims 11-12 and 15-17 will be examined; non-elected claims 1-10, 13-14, and 18-20 are withdrawn. The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites “a second memory cell having an identical structure as, and immediately neighboring, the first memory cell” in lines 7-8. It is unclear if “identical structure” refers to a mirrored/flipped structure, i.e. as best understood from figs. 8 and 11, having a second memory cell that appears to a mirror/flip of the first memory cell. For purposes of examination, the claims will be construed as mirrored/flipped structure.
Claim 15 recites “a half of the first dummy transistor” in line 1. As best understood from figs. 8 and 11, it appears that another half of the first dummy transistor is in the second memory cell. For purposes of examination, the claim will be construed as another half.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11, 15-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wahlstrom (US 2001/0035548).
Regarding claim 11, Wahlstrom discloses a device comprising:
a first memory cell (i.e. coupled to WLB1, BL1/BL2; fig. 13F) comprising:
a first data storage node (control node);
a write transistor (any transistor of the first memory cell is configurable for a write transistor, i.e. a write transistor coupled to WLB1, BL2; fig. 13F [0148]) comprising a source/drain region connected to the first data storage node (control node);
a read transistor (any transistor of the first memory cell is configurable for a read transistor, i.e. a read transistor coupled to WLB1, BL1; fig. 13F) comprising a gate connected to the first data storage node (control node);
a second memory cell (i.e. coupled to WLB0, BL1/BL2; fig. 13F) having an identical structure as, and immediately neighboring, the first memory cell (the second memory cell having any transistors configurable for a write/read transistor, i.e. a write transistor coupled to WLB0, BL1 and a read transistor coupled to WLB0, BL2; further, coupled to respective control node; fig. 13F); and
a first dummy transistor (a transistor coupled to dummy line DUM1/DUM0; fig. 13F) comprising at least a half (i.e. one of two) in the first memory cell (one of two source/drain region of the first dummy transistor is part of a shared node of the first memory cell, coupled to BL1/BL2, is essentially having half in the first memory cell; fig. 13F).
Regarding claim 15, Wahlstrom discloses the device of claim 11, wherein a half (i.e. another one of two) of the first dummy transistor is in the second memory cell (another one of the two source/drain region of the first dummy transistor is part of the shared node of the second memory cell, coupled to BL1/BL2, is essentially having half in the second memory cell; fig. 13F).
Regarding claim 16, Wahlstrom discloses the device of claim 11, wherein the first dummy transistor is configured to be turned off (i.e. inactive positive) throughout operation of the device (fig. 13G).
Allowable Subject Matter
Claim(s) 12, 17 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 12, the prior art fails to teach or suggest the claimed limitations, namely wherein the first dummy transistor comprising an additional gate connecting to the VDD line or the VSS line.
With respect to dependent claim 17, the prior art fails to teach or suggest the claimed limitations, namely wherein gates of the first dummy transistor and the second dummy transistor are interconnected.
The allowable claims are supported in at least fig. 8, 11 of the instant application.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to UYEN SMET whose telephone number is (571) 272-2267. The examiner can normally be reached M-F, 9 AM-5 PM.
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/UYEN SMET/
Primary Examiner, Art Unit 2824
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