Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/14/2024 and 10/07/2025 was filed before the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 9 and 10, the claim limitations “first thermal condition” and “second thermal condition” are vague and indefinite. The meets and bounds cannot be determined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIYAGAWA et al, JP 2008256678 A and further in view of Chang et al, US 20110156739 A1.
Miyagawa teaches:
1. A semiconductor device test system, comprising:
a semiconductor device (D) having a surface; Figure 3
a tester (SB) having a socket, the packaged multi-die semiconductor device disposed in the socket; (figure 3)
a thermal management component (100) engaging the semiconductor device (D) in the socket (SB), wherein the surface of the semiconductor device (D) interfaces with the thermal management component (100);
a coolant handling system (40) operable to provide a coolant to the thermal management component; and
a control system (250) operable to control a supply of coolant from the coolant handing system to the thermal management component. figure 6 and 7
2. The system of claim 1, wherein the coolant handling (40) system includes a plurality of pipes (40) extending to the thermal management component.
3. The system of claim 1, wherein the thermal management component (100) includes a sealed compartment (MC) interfacing the surface of the semiconductor device (D).
5. The system of claim 1, wherein in a top view, a sealed compartment of the thermal management component is centered on and comprised within a boundary defined by a die of the semiconductor device.
6. The system of claim 1, wherein the thermal management component (100) includes a plurality of sealed compartments (MC) for receiving coolant.
7. The system of claim 6, wherein the plurality of sealed compartments (MC) each interface the surface of the semiconductor device (D).
See figure 3 and 6, 7
9. A method of testing a semiconductor device, the method comprising: placing a packaged semiconductor (D) device on a tester (test unit);
engaging a thermal management component (100) with an upper surface of the packaged semiconductor device (d); and
testing (82) the packaged semiconductor device using the tester, and during the testing delivering a first thermal condition to a first region of the thermal management component while delivering a second thermal condition to a second region of the thermal management component, wherein the first thermal condition is different than the second thermal condition.. (fourth paragraph under “Tech Problem”)
In regards to the above claims 1-3,5-7 and 9, Miyagawa is silent to the semiconductor device being a packaged multi-die semiconductor device.
Chang teaches:
[0005] While such a wafer probe test with the die as part of a wafer is not a complete test of all functions of the die, it is helpful in eliminating the die which proves to be defective in such test. After that, the wafer is then sawed into individual dies, and each die is disposed on a substrate and then packaged as a semiconductor package. Complete functional testing is then undertaken on the die of the semiconductor package, and failed package are eliminated.
[0006] As for a multi-die semiconductor package, the testing procedure is similar to that described above. Assuming three dies passing the wafer probe test are packaged together as the multi-die semiconductor package, the overall functioning of the multi-die semiconductor package having three dies is tested. The multi-die semiconductor package is then eliminated if it fails such test. The failure may be due to the failure of one of the three dies, with the other two dies being properly functional. Due to the increased number of dies in the package, there is an increased possibility of including a die that, while passing the wafer probe test, would actually fail in more complete test for the multi-die semiconductor package, causing the entire device to be eliminated.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings of Chang, with the primary reference of Miyagawa, because for a multi-die semiconductor package, the testing procedure is similar. (para 006 Chang)
In regards to claims 4 and 8, Miyagawa fails to teach:
4. The system of claim 1, wherein the thermal management component includes a first compartment and a second compartment, wherein a pipe extends from the first compartment to the second compartment.
8. The system of claim 1, wherein the thermal management component includes at least one spray delivery.
In regards to claim 4:
Miyagawa teaches a temperature adjusting means for adjusting the ambient temperature of the semiconductor device mounted in each socket of each socket board to a predetermined test environment temperature, and each semiconductor device provided for each test unit and mounted in each socket.. In addition, the system includes two or more test chambers…. In the socket board circulation structure of the semiconductor device test system according to the fifth aspect of the present invention, an accessory device for supplying at least one of a power source, a refrigerant, and a heat medium to each of the test chambers is provided next to each other.. According to the sixteenth aspect of the present invention, at least one of each socket board loader and each socket board unloader includes heating / cooling means for heating or cooling the socket board to a predetermined temperature.
In regards to claim 8, Miyagawa teaches: The air cylinder 100 includes a plunger 104a that can be expanded and contracted with a predetermined stroke (for example, 5 mm), and the plunger104a is advanced downward by the control of a control device (control means: microcomputer (see FIG. 7)) 250.
Therefore, the arrangement of the chambers and associated piping and accessories such as a spray mechanism is merely a matter of design choice, since the testing apparatus means are similar. (see in Re Kuhle)
Claim Rejections - 35 USC § 103
Claim(s) 10-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyagawa and Chang as applied to claim 9 above, and further in view of Zhou et al, US 20230099805 A1.
Miyagawa fails to teach:
10. The method of claim 9, wherein the first thermal condition is delivered by supplying a first liquid coolant to the first region of the thermal management component and the second thermal condition is delivered by supplying a second liquid coolant to the second region of the thermal management component.
11. The method of claim 10, wherein the first liquid coolant is delivered by a spray and the second liquid coolant is delivered to a sealed compartment interfacing a portion of the packaged semiconductor device.
12. The method of claim 9, wherein the first region is a sealed compartment interfacing a first region of the upper surface of the packaged semiconductor device and wherein the second region is another sealed compartment interfacing a second region of the upper surface of the packaged semiconductor device.
13. The method of claim 12, wherein the first region of the upper surface of the packaged semiconductor device is a first die and the second region of the upper surface of the packaged semiconductor device is a second die.
14. The method of claim 9, further comprising:
determining a first temperature associated with the first region and determining a
second temperature associated with the second region, wherein the second
temperature is different than the first temperature.
15. The method of claim 9, further comprising:
setting a first target temperature for the first region, and
setting a second target temperature for the second region.
Miyagawa teaches a temperature adjusting means for adjusting the ambient temperature of the semiconductor device mounted in each socket of each socket board to a predetermined test environment temperature, and each semiconductor device provided for each test unit and mounted in each socket.. In addition, the system includes two or more test chambers…. In the socket board circulation structure of the semiconductor device test system according to the fifth aspect of the present invention, an accessory device for supplying at least one of a power source, a refrigerant, and a heat medium to each of the test chambers is provided next to each other.. According to the sixteenth aspect of the present invention, at least one of each socket board loader and each socket board unloader includes heating / cooling means for heating or cooling the socket board to a predetermined temperature.
The arrangement of the chambers and associated piping and accessories such as a spray mechanism is merely a matter of design choice, since the testing apparatus means are similar. (see in Re Kuhle)
Zhou teaches:
Abstract
A test socket for an IC chip includes a retainer positioned adjacent a load board, the retainer defining a plurality of apertures corresponding to contact pads on the load board; a plurality of contacts disposed in the plurality of apertures, the plurality of contacts configured to electrically couple the IC chip to the contact pads; a housing defining a chamber in fluid communication with an inlet, a liquid outlet, and a vapor outlet. The housing includes a body structure defining a plurality of cavities corresponding to the plurality of apertures and configured to receive the plurality of contacts therein, and a guide structure configured to receive the IC chip and position the IC chip in the chamber when engaged with the plurality of contacts. The chamber receives a two phase fluid coolant via the inlet to at least partially submerges the plurality of contacts in the two phase fluid coolant.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhou, with the primary references of Miyagawa and Chang, because after several iterations of testing, the test socket start to degrade but the liquid coolant improves the reliability of the test socket. (Zhou para 004)
In regards to claims 16-20.
Miyagawa teaches:
16. A method of adjusting a thermal environment of a semiconductor structure, the method comprising:
providing a semiconductor device (D);
providing a thermal management component (100) interfacing an upper surface of the semiconductor device (D);
Miyagawa fails to teach:
during an operation of the multi-die packaged semiconductor device, delivering a first liquid coolant to a first region of the thermal management component, wherein the first region overlies a first die of the multi-die packaged semiconductor device; and
delivering a second liquid coolant to a second region of the thermal management component, wherein the second region overlies a second die of the multi-die packaged semiconductor device, and wherein the delivering the second liquid coolant is concurrent with the delivering the first liquid coolant.
In regards to the above claim 16, Miyagawa is silent to the semiconductor device being a packaged multi-die semiconductor device.
Chang teaches:
[0005] While such a wafer probe test with the die as part of a wafer is not a complete test of all functions of the die, it is helpful in eliminating the die which proves to be defective in such test. After that, the wafer is then sawed into individual dies, and each die is disposed on a substrate and then packaged as a semiconductor package. Complete functional testing is then undertaken on the die of the semiconductor package, and failed package are eliminated.
[0006] As for a multi-die semiconductor package, the testing procedure is similar to that described above. Assuming three dies passing the wafer probe test are packaged together as the multi-die semiconductor package, the overall functioning of the multi-die semiconductor package having three dies is tested. The multi-die semiconductor package is then eliminated if it fails such test. The failure may be due to the failure of one of the three dies, with the other two dies being properly functional. Due to the increased number of dies in the package, there is an increased possibility of including a die that, while passing the wafer probe test, would actually fail in more complete test for the multi-die semiconductor package, causing the entire device to be eliminated.
17. The method of claim 16, wherein the first region of the thermal management
component is a first sealed compartment, wherein a side of the first sealed compartment is defined by an upper surface of the first die.
18. The method of claim 17, wherein the second region of the thermal management component includes a spray nozzle disposed over an upper surface of the second die.
19. The method of claim 17, wherein the second region of the thermal management
component includes a second sealed compartment, wherein a side of the second sealed compartment is defined by an upper surface of the second die.
20. The method of claim 16, further comprising:
delivering a third liquid coolant to a third region of the thermal management component,
wherein the third region overlies a third die of the multi-die packaged semiconductor device.
Miyagawa teaches a temperature adjusting means for adjusting the ambient temperature of the semiconductor device mounted in each socket of each socket board to a predetermined test environment temperature, and each semiconductor device provided for each test unit and mounted in each socket.. In addition, the system includes two or more test chambers…. In the socket board circulation structure of the semiconductor device test system according to the fifth aspect of the present invention, an accessory device for supplying at least one of a power source, a refrigerant, and a heat medium to each of the test chambers is provided next to each other.. According to the sixteenth aspect of the present invention, at least one of each socket board loader and each socket board unloader includes heating / cooling means for heating or cooling the socket board to a predetermined temperature.
The arrangement of the chambers and associated piping and accessories such as a spray mechanism is merely a matter of design choice, since the testing apparatus means are similar. (see in Re Kuhle)
Chang teaches:
[0005] While such a wafer probe test with the die as part of a wafer is not a complete test of all functions of the die, it is helpful in eliminating the die which proves to be defective in such test. After that, the wafer is then sawed into individual dies, and each die is disposed on a substrate and then packaged as a semiconductor package. Complete functional testing is then undertaken on the die of the semiconductor package, and failed package are eliminated.
[0006] As for a multi-die semiconductor package, the testing procedure is similar to that described above. Assuming three dies passing the wafer probe test are packaged together as the multi-die semiconductor package, the overall functioning of the multi-die semiconductor package having three dies is tested. The multi-die semiconductor package is then eliminated if it fails such test. The failure may be due to the failure of one of the three dies, with the other two dies being properly functional. Due to the increased number of dies in the package, there is an increased possibility of including a die that, while passing the wafer probe test, would actually fail in more complete test for the multi-die semiconductor package, causing the entire device to be eliminated.
Zhou teaches:
Abstract
A test socket for an IC chip includes a retainer positioned adjacent a load board, the retainer defining a plurality of apertures corresponding to contact pads on the load board; a plurality of contacts disposed in the plurality of apertures, the plurality of contacts configured to electrically couple the IC chip to the contact pads; a housing defining a chamber in fluid communication with an inlet, a liquid outlet, and a vapor outlet. The housing includes a body structure defining a plurality of cavities corresponding to the plurality of apertures and configured to receive the plurality of contacts therein, and a guide structure configured to receive the IC chip and position the IC chip in the chamber when engaged with the plurality of contacts. The chamber receives a two phase fluid coolant via the inlet to at least partially submerges the plurality of contacts in the two phase fluid coolant.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhou, with the primary reference of Miyagawa and Chang, because after several iterations of testing, the test socket start to degrade but the liquid coolant improves the reliability of the test socket. (Zhou para 004)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Mahoney et al, US 7138811 B1 teaches:
(para 11) FIG. 3 is an exploded perspective view and a simplified cross-sectional side view showing a portion of a conventional low-temperature testing arrangement 300 that utilizes test system 100 (described above). The conventional low-temperature testing arrangement 300 generally includes device tester 110, a low-temperature handler system 350, and load board 120, which connect between device tester 110 and handler system 350 during low-temperature testing procedures. Low-temperature handler system 350 includes an insulated box 352 connected to a cooling system (not shown), and a device handling mechanism (handler) 355 mounted inside of insulated box 352. An opening 357 is provided in a side wall of insulated box 352 through which test sockets 127 of handler board 120 are exposed to the cool dry environment maintained inside insulated box 352. Device handling mechanism 355 (partially shown) is an expensive precise robot including an arm for moving a DUT from a storage location (e.g., a shipping tray) to the test socket 127 during test procedures. The storage location is also inside of insulated box 352 so that the DUTs are maintained at a desired low temperature throughout the test procedures. Conventional systems meeting the description of low-temperature handler system 350 are produced, for example, by Delta Design of San Diego, Calif., USA..
Dau et al, US 20170131348 A1 teaches:
[0002] The present invention relates to an electrical/mechanical interface apparatus, and in particular, to a multi-die interface apparatus for semiconductor testing and method of manufacturing same.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/Primary Examiner, Art Unit 2893
Prosecution Insights