DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the sacrificial layers must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4-6, 10, 16, 17 is/are rejected under 35 U.S.C. 102(2) as being anticipated by Chen et al. (US-20250031435-A; Chen).
Regarding claim 1, Chen discloses a device, comprising: a transistor including: a first source/drain region (Fig. 9, 108L; ¶45) ; a second source/drain region (Fig. 9, 108L; ¶45) ; a plurality of stacked channels (Fig. 9, 66 stack; ¶32)each extending in a first lateral direction (into the page) between the first source/drain region and the second source/drain region and having a first width in a second lateral direction (left/right); and a hard mask structure (Fig. 9, 84/86; ¶31) directly above the stacked channels and having a second width in the second direction smaller than the first width.(clear from drawing)
Regarding claim 2, Chen discloses the device of claim 1, wherein the hard mask structure (Fig. 4/9, 74/76 becomes 84/86; ¶31) and the channels (Fig. 9, 66 stack; ¶32) each have a same length in the first direction.
When 74/76 is etched from sidewalls of the stack, and when the trenches are etched 74/76 become 84/86.
Regarding claim 4, Chen discloses the device of claim 1, wherein each channel (Fig. 9, 66 stack; ¶27/32) includes a respective epitaxial semiconductor layer (¶27) extending laterally outside the hard mask structure (Fig. 9, 84/86; ¶31) in the second direction. (left/right)
Regarding claim 5, Chen discloses the device of claim 4, wherein the epitaxial semiconductor layer (Fig. 9, 66 stack; ¶47 silicon) is a different material than the first source/drain region. (Fig. 9, 108L; ¶47 carbon doped silicon)
Regarding claim 6, Chen discloses the device of claim 4, wherein the epitaxial semiconductor layer (Fig. 9, 66 stack; ¶47 silicon) is an intrinsic semiconductor material.
Regarding claim 10, Chen discloses the device of claim 1, wherein a bottom surface of the hard mask structure (Fig. 9, 84/86; ¶31) is higher than a top surface of the first source/drain region. (Fig. 9, 108L; ¶47)
Regarding claim 16, Chen discloses a method, comprising: forming a hard mask structure (Fig. 5, 84/86; ¶31) by patterning a hard mask layer over a stack of semiconductor layers (Fig. 5, 64/66; ¶32); forming (etching; ¶33), from the stack of semiconductor layers, a plurality of stacked channels (Fig. 6 ; ¶33) of a transistor by patterning the stack of semiconductor layers in a presence of the hard mask structure; forming a first source/drain region (Fig. 5, 108L; ¶45) and a second source/drain region (Fig. 5, 108L; ¶45) of the transistor by performing a first epitaxial growth process, each channel extending in a first lateral direction between the first source/drain region and the second source/drain region; and forming, on each channel, an epitaxial semiconductor layer (Fig. 5, 108U; ¶45) by performing a second epitaxial growth process after the first epitaxial growth process in a presence of the hard mask.(Fig. 5, 84/86; ¶31)
Regarding claim 17, Chen discloses the method of claim 16, comprising: removing the hard mask structure (Fig. 10, 84/86; ¶60); and forming a gate metal (Fig. 12B, 134U; ¶31) wrapped around each of the channels after removing the hard mask structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7, 11, 14, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US-20250031435-A; Chen) in view of Liaw (US-20220336460-A1; Liaw).
Regarding claim 7, Chen discloses the device of claim 4, but is silent on wherein each channel has a dumbbell shape.
Liaw discloses a similar device comprising a dumbbell shaped channel (Fig. 14B, 220A; ¶42).
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to adjust the dimensions of the channel layer for optimized device reliability. Also, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
MPEP 2144.04 (IV)(A)
Regarding claim 11, Chen discloses a device, comprising: a transistor including: a first source/drain region (Fig. 1, 108L; ¶11); a second source/drain region (Fig. 1, SECOND 108L; ¶11); and a plurality of stacked channels (Fig. 1, 66; ¶11) each extending in a first lateral direction (A) between the first source/drain region and the second source/drain region and having a first end region adjacent to the first source/drain region, a second end region adjacent to the second source/drain region, and a middle region between the first and second end regions, wherein the first and second end regions each have a first width in a second lateral direction (B) transverse to the first lateral direction (A), but is silent on wherein the middle region has a second width larger than the first width in the second lateral direction.
Liaw discloses a transistor device comprising a channel having a middle region (Fig. 14B, 220A-CENTER; ¶42) with second width larger than the first width (Fig. 14B, 220A-END; ¶42) in the second lateral direction.(Y)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to adjust the dimensions of the channel layer for optimized device reliability. Also, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device.
MPEP 2144.04 (IV)(A)
Regarding claim 14, Chen in view of Liaw discloses the device of claim 11, wherein the transistor includes: a gate dielectric layer (Fig. 1, 132; ¶11 Chen) in contact with the middle region of each channel (Fig. 1, 66; ¶11 Chen) but not in contact with the first and second end regions of each channel; and a metal (Fig. 1, 134L; ¶11 Chen) wrapped around the middle region of each channel.
Regarding claim 20, Chen in view of Liaw discloses the method of claim 16, wherein after the second epitaxial growth process the channels a middle portion of each channel is wider in a second lateral direction transverse to the first lateral direction than are first and second portions of each channel, the first end portion adjacent to the first source/drain region, the second end portion adjacent to the second source/drain region.
This claim describes the dumbbell shaped channel region claimed above.
Liaw discloses a transistor device comprising a channel having a middle region (Fig. 14B, 220A-CENTER; ¶42) with second width larger than the first width (Fig. 14B, 220A-END; ¶42) in the second lateral direction.(Y)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to adjust the dimensions of the channel layer for optimized device reliability. Also, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US-20250031435-A; Chen).
Regarding claim 8, Chen discloses the device of claim 4, but is silent on wherein the epitaxial semiconductor layer is rounded.
However, this is simply a change in the shape of a feature disclosed by the cited art. Therefore before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to change the shape the channel layer because where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device.
MPEP 2144.04 (IV)(A)
Allowable Subject Matter
Claims 3, 9, 12, 13,15, 18, and 19 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 15 is objected to being dependent on claim 13
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limited, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding claim 3, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the transistor includes a gate electrode wrapped around each of the channels and the hard mask structure.”, as recited in Claim 3, with the remaining features.
Regarding claim 9, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " comprising a gate dielectric layer wrapped around each of the channels and the hard mask structure, … wherein the gate dielectric is positioned between the hard mask structure and the gate metal.”, as recited in Claim 9, with the remaining features.
Regarding claim 12, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the transistor includes a hard mask structure directly above the stacked channels and having a uniform width in the second lateral direction equal to the first width and a length in the first lateral direction equal to a length of each of the channels.”, as recited in Claim 12, with the remaining features.
Regarding claim 13, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the transistor includes a gate metal wrapped around each of the channels and the hard mask structure.”, as recited in Claim 13, with the remaining features.
Regarding claim 18, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " a gate metal of the transistor wrapped around each of the channels and the hard mask structure.”, as recited in Claim 18, with the remaining features.
Regarding claim 19, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " after the first epitaxial growth process, inner spacers between the channels and in contact with the first source/drain region; removing sacrificial semiconductor structures from between the channels after forming the inner spacers; forming dielectric plugs in place of the sacrificial semiconductor structures between the channels; preforming the second epitaxial growth process in a presence of the dielectric plugs; removing the dielectric plugs; and forming a gate metal of the transistor in place of the dielectric plugs and wrapped around each of the channels.”, as recited in Claim 19, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
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/LAWRENCE C TYNES JR./ Examiner, Art Unit 2899
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