DETAILED ACTION
This action is responsive to the following communications: the Request for Continued Examination (with claim amendment) filed on May 18, 2026.
Claims 1 and 3-8 are pending. Claim 1 is amended. Claim 2 is canceled. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 18, 2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claims 1 and 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Mojumder et al. (20160064068) in view of Houston (US 20110044094).
Regarding independent claim 1, Mojumder et al. disclose a three-port SRAM circuit [Fig. 3-4, para. 39], comprising a first P-type transistor (P1) [Fig. 4: 408], a second P-type transistor (P2) [Fig. 4: 410], a third P-type transistor (P3) [Fig. 4: 306], a fourth P-type transistor (P4) [Fig. 4: 304], a first N-type transistor (N1) [Fig. 4: 412], a second N-type transistor (N2) [Fig. 4: 414], a third N-type transistor (N3) [Fig. 4: 416], a fourth N-type transistor (N4) [Fig. 4: 418], a fifth transistor [Fig. 4: 356], and a sixth transistor [Fig. 4: 354, para. 40-42], wherein
source terminals of the first P-type transistor (P1) [Fig. 4: 408] and the second P-type transistor (P2) [Fig. 4: 410] are connected to an operating voltage (Vdd) [see Fig. 4];
a gate terminal of the first P-type transistor (P1) [Fig. 4: 408], a drain terminal of the second P-type transistor (P2) [Fig. 4: 410], a gate terminal of the first N-type transistor (N1) [Fig. 4: 412], a drain terminal of the second N-type transistor (N2) [Fig. 4: 414], and a gate terminal of the fifth transistor (N5) [Fig. 4: 356] are connected together to a second node (n2) [see Examiner Markup Mojumder et al.’s Figure 4: n2];
a gate terminal of the second P-type transistor (P2) [Fig. 4: 410], a drain terminal of the first P-type transistor (P1) [Fig. 4: 408], a gate terminal of the second N-type transistor (N2) [Fig. 4: 414], a drain terminal of the first N-type transistor (N1) [Fig. 4: 412], and a gate terminal of the third P-type transistor (P3) [Fig. 4: 306] are connected together to a first node (n1) [see Examiner Markup Mojumder et al.’s Figure 4: n1];
gate terminals of the third N-type transistor (N3) [Fig. 4: 416] and the fourth N-type transistor (N4) [Fig. 4: 418] are connected to a word line A (A-WL) [see Fig. 4, gates of the NMOS transistors 416, 418 are coupled to a write word line (WWL), para. 40];
source and drain terminals of the third N-type transistor (N3) [Fig. 4: 416] are respectively connected to the first node (n1) [see Examiner Markup Mojumder et al.’s Figure 4: n1] and a first bit line (BL1) [Fig. 4: WBL1, a drain of the NMOS transistor 416 is coupled to a first write bit line (WBL1), para. 40];
source and drain terminals of the fourth N-type transistor (N4) [Fig. 4: 418] are respectively connected to the second node (n2) [see Examiner Markup Mojumder et al.’s Figure 4: n2] and a second bit line (BL2) [Fig. 4: WBL2, a drain of the NMOS transistor 418 is coupled to a first write bit line (WBL2), para. 40];
a gate terminal of the fourth P-type transistor (P4) [Fig. 4: 304] is connected to a word line C (C-WL) [Fig. 4: RWL1, a gate of the PMOS transistor 304 is coupled to a first read word line (RWL1), para. 35], and one terminal of its source and drain terminals is connected to a source terminal of the third P-type transistor (P3) [Fig. 4: 306, a source of the PMOS transistor 306 is coupled to a drain of the PMOS transistor 304, para. 35] and the other terminal is connected to a port C bit line [Fig. 4: RBL1, a source of the PMOS transistor 304 is coupled to a first read bit line (RBL1), para. 35];
a gate terminal of the sixth transistor [Fig. 4: 354] is connected to a word line B (B-WL) [Fig. 4: RWL2, a gate of the PMOS transistor 354 is coupled to a second read word line (RWL2), para. 36], and one terminal of its source and drain terminals is connected to a drain terminal of the fifth transistor [Fig. 4: 356, a source of the PMOS transistor 356 is coupled to a drain of the PMOS transistor 354, para. 36] and the other terminal is connected to a port B bit line [Fig. 4: RBL2, a source of the PMOS transistor 354 is coupled to a second read bit line (RBL2), para. 36]; and
a source terminal of the first N-type transistor (N1), a source terminal of the second N-type transistor (N2), a drain terminal of the third P-type transistor (P3), and a source terminal of the fifth transistor are connected to a common ground (Vss) [see Fig. 4, the drain of the PMOS transistors 306, 356 and the source of the NMOS transistors 412, 414 are coupled to ground, para. 35-36 as well as para. 40];
the word line A (A-WL) [Fig. 4: WWL], the first bit line (BL1) [Fig. 4: WBL1], and the second bit line (BL2) [Fig. 4: WBL2] belong to a port A [Fig. 4: the write port 332, para. 40];
the word line C (C-WL) [Fig. 4: RWL1] and the port C bit line [Fig. 4: RBL1] belong to a port C [Fig. 4: the first read port 302, para. 35]; and
the word line B (B-WL) [Fig. 4: RWL2] and the port B bit line [Fig. 4: RBL2] belong to a port B [Fig. 4: the second read port 352, para. 36].
However, Mojumder et al. disclose the fifth transistor [Fig. 4: 356], and the sixth transistor [Fig. 4: 354, para. 40-42] are P-type transistors [para. 36], not the N-type transistors. In other words, Mojumder et al. teach the left-side read buffer is made of P-type transistors, not N-type transistors (i.e., the fifth N-type transistor (N5) and the sixth N-type transistor (N6) as claimed). Further, Mojumder et al. are silent with respect to storage states of the first node (n1) and the second node (n2) are opposite, so that the third P-type transistor (P3) with the gate terminal thereof corresponding to the first node (n1) and the fifth N-type transistor (N5) with the gate terminal thereof corresponding to the second node (n2) can be on/off synchronously; when in a read state, the sixth N-type transistor (N6) and the fourth P-type transistor (P4) are both on, the port C bit line (C-BL) and the port B bit line (B-BL) can be held/discharge synchronously.
Houston teaches an SRAM cell [Fig. 2] contains a pair of cross-coupled inverters (2002) which includes a bit-side data node (2004) and a bit-bar-side data node (2006). The SRAM cell (2000) further contains a first read buffer (2022) and a second read buffer (2024). The first read buffer (2022) includes a first access transistor (2026) and a first read buffer driver transistor (2028) that are depicted as NMOS transistors [para. 24-25]. Houston explains, “Each SRAM cell also contains two read buffers . . . “[E]ach read buffer may be independently formed with NMOS or PMOS transistors.” [para. 22]. Houston notes that the left side read buffer composed of access transistors 2025 and read buffer driver transistor 2028 are illustrated in Figure 2 as NMOS transistors, “but may be PMOS transistors” [para. 25]. In other words, Houston teaches that any read buffer may be made of PMOS transistors or NMOS transistors, at the discretion of those skilled in the art of SRAM.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Houston to the teachings of Mojumder et al. such that retaining one of Mojumder et al.’s read ports as PMOS read buffer while implementing the other read port of Mojumder et al. as Houston’s NMOS read buffer to achieve the predictable, routine design choice of mixed-polarity read paths and standard NMOS write access while preserving Mojumder et al.’s 10T SRAM architecture and read-sensing scheme. As to the limitation that the storage states of node n1 and node n2 are opposite, when the PMOS read buffer taught by Mojumder et al. is connected to node n1 and the NMOS read buffer taught by Houston is connected to node n2, the claimed synchronous operation is the predictable result of the proposed structure. In an SRAM latch, the two storage nodes are complementary. If a PMOS read transistor is connected to node n1 and an NMOS read transistor is connected to the opposite node n2, then when n1 is low and n2 is high, the PMOS read transistor is on and the NMOS read transistor is also on. When n1 is high and n2 is low, both transistors are off. Therefore, in read state, when transistors P4 and N6 are enabled, the port C bit line (C-BL) and the port B bit line (B-BL) are held or discharge synchronously.
Regarding claim 3, Mojumder et al. in combination with Houston teach the limitations with respect to claim 1.
Furthermore, Mojumder et al. disclose wherein
the third P-type transistor (P3) and the fourth P-type transistor (P4) are field effect transistors [the first read port 302 includes a PMOS transistor 304 (e.g., a pass gate) having a SiGe channel coupled to another PMOS transistor 306 having a SiGe channel, para. 35].
Houston discloses the fifth N-type transistor (N5) and the sixth N-type transistor (N6) are field effect transistors [The first access transistor (2026) and the first read buffer driver transistor (2028) are depicted in FIG. 2 as NMOS transistors, para. 25. The terms "driver transistor" and "access transistor" are understood to refer to a field effect transistor such as a metal oxide semiconductor (MOS) transistor, para. 15 and 17].
Regarding claim 4, Mojumder et al. in combination with Houston teach the limitations with respect to claim 1.
Furthermore, Mojumder et al. disclose wherein
the third P-type transistor (P3), the fourth P-type transistor (P4) are junction field effect transistors or metal oxide semiconductor field effect transistors [the first read port 302 includes a p-type metal oxide semiconductor (PMOS) transistor 304 (e.g., a pass gate) having a SiGe channel coupled to another PMOS transistor 306 having a SiGe channel, para. 4 as well as para. 35].
Houston discloses the fifth N-type transistor (N5), and the sixth N-type transistor (N6) are junction field effect transistors or metal oxide semiconductor field effect transistors [The first access transistor (2026) and the first read buffer driver transistor (2028) are depicted in FIG. 2 as NMOS transistors, para. 25. The terms "driver transistor" and "access transistor" are understood to refer to a field effect transistor such as a metal oxide semiconductor (MOS) transistor, para. 15 and 17].
Regarding claim 5, Mojumder et al. in combination with Houston teach the limitations with respect to claim 1.
Furthermore, Mojumder et al. disclose wherein
the first P-type transistor (P1) and the second P-type transistor (P2) are PMOS transistors [see Fig. 4, the write port 332 includes a PMOS transistor 408 (e.g., a pull-up transistor) having a SiGe channel and another PMOS transistor 410 (e.g., a pull-up transistor) having a SiGe channel, para. 40]; and
the first N-type transistor (N1), the second N-type transistor (N2), the third N-type transistor (N3), and the fourth N-type transistor (N4) are NMOS transistors [see Fig. 4, the write port 332 also includes an NMOS transistor 412 (e.g., a pull-down transistor), an NMOS transistor 414, an NMOS transistor 416 (e.g., a pass gate) and an NMOS transistor 418 (e.g., a pass gate), para. 40].
Regarding claim 6, Mojumder et al. in combination with Houston teach the limitations with respect to claim 1.
Furthermore, Mojumder et al. disclose wherein
the source terminal of the fourth P-type transistor (P4) is connected to the port C bit line [see Fig. 4, a source of the PMOS transistor 304 is coupled to a first read bit line (RBL1), para. 35], and the drain terminal of same is connected to the source terminal of the third P-type transistor (P3) [see Fig. 4, a source of the PMOS transistor 306 is coupled to a drain of the PMOS transistor 304, para. 35].
Houston discloses the source terminal of the sixth N-type transistor (N6) is connected to the drain terminal of the fifth N-type transistor (N5) [see Fig. 2, a second source/drain node of the first access transistor (2026) is connected to a drain node of the first read buffer driver transistor (2028), para. 25], and the drain terminal of same is connected to the port B bit line [see Fig. 2, a first source/drain node of the first access transistor (2026) is connected to a first read data line (2032), para. 25. The terms "bit line" and "bit-bar line" are understood to refer to data lines connected to passgate transistors or read buffers in a column of SRAM cells, para. 18].
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Mojumder et al. (20160064068) in view of Houston (US 20110044094) as applied to claim 1 above and further in view of Hsu et al. (US 20180366469).
Regarding claim 7, Mojumder et al. in combination with Houston teach the limitations with respect to claim 1.
However, Mojumder et al. in combination with Houston are silent with respect to wherein a chip layout structure thereof is as follows:
the first P-type transistor (P1) is located on the left side of the second P-type transistor (P2);
the first N-type transistor (N1) and the third N-type transistor (N3) are located on the left side of the first P-type transistor (P1), and the first N-type transistor (N1) is located on the front side of the third N-type transistor (N3);
the third P-type transistor (P3) and the fourth P-type transistor (P4) are located on the left side of the first N-type transistor (N1) and the third N-type transistor (N3), and the third P-type transistor (P3) is located on the front side of the fourth P-type transistor (P4);
the second N-type transistor (N2) and the fourth N-type transistor (N4) are located on the right side of the second P-type transistor (P2), and the second N-type transistor (N2) is located on the rear side of the fourth N-type transistor (N4); and
the fifth N-type transistor (N5) and the sixth N-type transistor (N6) are located on the right side of the second N-type transistor (N2) and the fourth N-type transistor (N4), and the fifth N-type transistor (N5) is located on the rear side of the sixth N-type transistor (N6).
Hsu et al. teach a chip layout structure [see Fig. 1B] thereof is as follows:
the first P-type transistor (P1) [Fig. 1B: Tr2] is located on the left side of the second P-type transistor (P2) [Fig. 1B: Tr3];
the first N-type transistor (N1) [Fig. 1B: Tr1] and the third N-type transistor (N3) [Fig. 1B: Tr7] are located on the left side of the first P-type transistor (P1) [see Fig. 1B: Tr2], and the first N-type transistor (N1) is located on the front side of the third N-type transistor (N3) [see Fig. 1B with respect to Fig. 1A].
the second N-type transistor (N2) [Fig. 1B: Tr4] and the fourth N-type transistor (N4) [Fig. 1B: Tr8] are located on the right side of the second P-type transistor (P2) [Fig. 1B: Tr3], and the second N-type transistor (N2) is located on the rear side of the fourth N-type transistor (N4) [see Fig. 1B with respect to Fig. 1A]; and
the fifth N-type transistor (N5) [Fig. 1B: Tr5] and the sixth N-type transistor (N6) [Fig. 1B: Tr6] are located on the right side of the second N-type transistor (N2) [Fig. 1B: Tr4] and the fourth N-type transistor (N4) [Fig. 1B: Tr8], and the fifth N-type transistor (N5) is located on the rear side of the sixth N-type transistor (N6) [see Fig. 1B with respect to Fig. 1A].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Hsu et al. to the teachings of Mojumder et al. in combination with Houston such that implementing the three-port SRAM of Mojumder et al. in combination with Houston using chip layout as taught by Hsu et al. to achieve the predictable use of known layout techniques to realize the known three-port SRAM function.
Regarding claim 8, Mojumder et al. in combination with Houston and Hsu et al. teach the limitations with respect to claim 7.
Furthermore, Hsu et al. disclose wherein the chip layout structure [Fig. 1B] thereof is as follows:
center lines of gate polysilicon of the first P-type transistor (P1), the first N-type transistor (N1), the third P-type transistor (P3), the fourth N-type transistor (N4), the sixth N-type transistor (N6) in the horizontal direction are on the same straight line [see Fig. 1B, the gates G1, G2, G3, G4, G5, G6, G7, and G8 are oriented lengthwise along the “x” direction with the gates G1, G2, G8, and G6 are aligned on a straight line, para. 30]; and
center lines of gate polysilicon of the second P-type transistor (P2), the third N-type transistor (N3), the fourth P-type transistor (P4), the second N-type transistor (N2), and the fifth N-type transistor (N5) in the horizontal direction are on the same straight line [see Fig. 1B, the gates G7, G3, G4, and the G5 are aligned on another straight line, para. 30].
Response to Arguments
Applicant's arguments filed with respect to independent claim 1 have been fully considered but they are not persuasive.
Applicant argues the obviousness rejection over the combination of Mojumder and Houston is improper because Mojumder’s port C transistors do not have a doping type opposite to the port B transistors. Instead, Mojumder show both of their left-side read buffer and right-side read buffer are made of PMOS transistors. In other words, applicant asserts that Mojumder does not teach “a sixth N-type transistor (N6)” and “fifth N-type transistor (N5)” as connected to port B, as required by claim 1.
Applicant’s argument is not persuasive because the rejection was an obviousness rejection over not just Mujumber, but over the combination of Mojumder and Houston. Mojumber was not relied upon for teaching the two read buffers having opposite doping. Houston was relied upon for teaching or suggesting the read buffers be made independently with PMOS or NMOS (see Houston para. 22, 25; see also Final Act. Pages 6-7). One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references [see MPEP 2145 IV].
Applicant also argues the obviousness rejection over the combination of Mojumder and Houston is improper because, according to applicant, Houston’s disclosure that “each buffer may be independently formed with NMOS or PMOS transistors” can only be interpreted as both read buffers may be made entirely of NMOS or both read buffers may be made entirely of PMOS (Remarks 5-6). To support this argument, applicant asserts that Houston illustrates their two read buffers are entirely NMOS (Figures 2 and 4).
Applicant’s argument is not persuasive. Although Houston’s Figure 2 shows both read buffers (2022 and 2024) as being formed of NMOS transistors, Houston explains in paragraph 25 that the “The first read buffer (2022) includes a first access transistor (2026) and a first read buffer driver transistor (2028). The first access transistor (2026) and the first read buffer driver transistor (2028) are depicted in FIG. 2 as NMOS transistors, but may be PMOS transistors in other embodiments.” In other words, applicant’s assertion that Houston’s sentence, “each buffer may be independently formed with NMOS or PMOS transistors” must mean both read buffers may be made entirely of NMOS or both read buffers may be made entirely of PMOS, does not appear to be correct because Houston actually discloses for their 10T-SRAM cell illustrated in Figure 2, their left-side read buffer may alternately be made of PMOS transistors.
Applicant finally argues that the last clauses of independent claim 1 are not disclosed. These arguments are not persuasive for the following reasons:
For SRAM, the two nodes are always logically opposite, and applicant’s asserted claim limitation “storage states of the first node (n1) and the second node n2) are opposite” is an inherent property of the storage state of the SRAM illustrated by both Mojumder and Houston’s SRAM cells that are formed by cross-coupled inverters;
The gate terminal of the third P-type transistor (i.e., read driver of the PMOS read buffer) corresponding to the first node and the fifth N-type transistor (i.e., read driver of the NMOS read buffer) corresponding to the second node can be on/off synchronously because the combination of Mojumder and Houston teach the same involved circuitry (i.e., left-side PMOS read buffer and right-side NMOS read buffer for SRAM) and would operate the same way under normal operation; and
When in a read state, the sixth N-type transistor (i.e., the read access transistor for NMOS read buffer) and fourth P-type transistor (i.e., read access transistor for PMOS read buffer) are both on, the port C bit line and port B bit line can be held or discharged synchronously, because the combination of Mojumder and Houston teach the same involved circuitry (i.e., left-side PMOS read buffer and right-side NMOS read buffer for SRAM) and would operate the same way under normal operation. Additionally, both Mojumder and Houston illustrate the read access transistors for both read ports have separate read word line control (Mojumber Fig. 4: RWL2 and RWL1; see Houston Fig. 2: 2030 and 2040), and even though there are independent signals to control the read access transistors, these word line control signals can also be activated at the same time. When both read buffers are activated, both bit lines will either hold or discharge depending upon the data state.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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