DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on February 3, 2026 and the Foreign Priority papers retrieved on August 25, 2023.
Claims 1 and 3-8 are pending. Claims 1, 3 and 6 are amended. Claim 2 is canceled. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings were received on February 3, 2026. These drawings are acceptable.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claims 1 and 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Mojumder et al. (20160064068) in view of Houston (US 20110044094).
Regarding independent claim 1, Mojumder et al. disclose a three-port SRAM circuit [Fig. 3-4, para. 39], comprising a first P-type transistor (P1) [Fig. 4: 408], a second P-type transistor (P2) [Fig. 4: 410], a third P-type transistor (P3) [Fig. 4: 306], a fourth P-type transistor (P4) [Fig. 4: 304], a first N-type transistor (N1) [Fig. 4: 412], a second N-type transistor (N2) [Fig. 4: 414], a third N-type transistor (N3) [Fig. 4: 416], a fourth N-type transistor (N4) [Fig. 4: 418], a fifth transistor [Fig. 4: 356], and a sixth transistor [Fig. 4: 354, para. 40-42], wherein
source terminals of the first P-type transistor (P1) [Fig. 4: 408] and the second P-type transistor (P2) [Fig. 4: 410] are connected to an operating voltage (Vdd) [see Fig. 4];
a gate terminal of the first P-type transistor (P1) [Fig. 4: 408], a drain terminal of the second P-type transistor (P2) [Fig. 4: 410], a gate terminal of the first N-type transistor (N1) [Fig. 4: 412], a drain terminal of the second N-type transistor (N2) [Fig. 4: 414], and a gate terminal of the fifth transistor (N5) [Fig. 4: 356] are connected together to a second node (n2) [see Examiner Markup Mojumder et al.’s Figure 4: n2];
a gate terminal of the second P-type transistor (P2) [Fig. 4: 410], a drain terminal of the first P-type transistor (P1) [Fig. 4: 408], a gate terminal of the second N-type transistor (N2) [Fig. 4: 414], a drain terminal of the first N-type transistor (N1) [Fig. 4: 412], and a gate terminal of the third P-type transistor (P3) [Fig. 4: 306] are connected together to a first node (n1) [see Examiner Markup Mojumder et al.’s Figure 4: n1];
gate terminals of the third N-type transistor (N3) [Fig. 4: 416] and the fourth N-type transistor (N4) [Fig. 4: 418] are connected to a word line A (A-WL) [see Fig. 4, gates of the NMOS transistors 416, 418 are coupled to a write word line (WWL), para. 40];
source and drain terminals of the third N-type transistor (N3) [Fig. 4: 416] are respectively connected to the first node (n1) [see Examiner Markup Mojumder et al.’s Figure 4: n1] and a first bit line (BL1) [Fig. 4: WBL1, a drain of the NMOS transistor 416 is coupled to a first write bit line (WBL1), para. 40];
source and drain terminals of the fourth N-type transistor (N4) [Fig. 4: 418] are respectively connected to the second node (n2) [see Examiner Markup Mojumder et al.’s Figure 4: n2] and a second bit line (BL2) [Fig. 4: WBL2, a drain of the NMOS transistor 418 is coupled to a first write bit line (WBL2), para. 40];
a gate terminal of the fourth P-type transistor (P4) [Fig. 4: 304] is connected to a word line C (C-WL) [Fig. 4: RWL1, a gate of the PMOS transistor 304 is coupled to a first read word line (RWL1), para. 35], and one terminal of its source and drain terminals is connected to a source terminal of the third P-type transistor (P3) [Fig. 4: 306, a source of the PMOS transistor 306 is coupled to a drain of the PMOS transistor 304, para. 35] and the other terminal is connected to a port C bit line [Fig. 4: RBL1, a source of the PMOS transistor 304 is coupled to a first read bit line (RBL1), para. 35];
a gate terminal of the sixth transistor [Fig. 4: 354] is connected to a word line B (B-WL) [Fig. 4: RWL2, a gate of the PMOS transistor 354 is coupled to a second read word line (RWL2), para. 36], and one terminal of its source and drain terminals is connected to a drain terminal of the fifth transistor [Fig. 4: 356, a source of the PMOS transistor 356 is coupled to a drain of the PMOS transistor 354, para. 36] and the other terminal is connected to a port B bit line [Fig. 4: RBL2, a source of the PMOS transistor 354 is coupled to a second read bit line (RBL2), para. 36]; and
a source terminal of the first N-type transistor (N1), a source terminal of the second N-type transistor (N2), a drain terminal of the third P-type transistor (P3), and a source terminal of the fifth transistor are connected to a common ground (Vss) [see Fig. 4, the drain of the PMOS transistors 306, 356 and the source of the NMOS transistors 412, 414 are coupled to ground, para. 35-36 as well as para. 40];
the word line A (A-WL) [Fig. 4: WWL], the first bit line (BL1) [Fig. 4: WBL1], and the second bit line (BL2) [Fig. 4: WBL2] belong to a port A [Fig. 4: the write port 332, para. 40];
the word line C (C-WL) [Fig. 4: RWL1] and the port C bit line [Fig. 4: RBL1] belong to a port C [Fig. 4: the first read port 302, para. 35]; and
the word line B (B-WL) [Fig. 4: RWL2] and the port B bit line [Fig. 4: RBL2] belong to a port B [Fig. 4: the second read port 352, para. 36].
However, Mojumder et al. disclose the fifth transistor [Fig. 4: 356], and the sixth transistor [Fig. 4: 354, para. 40-42] are P-type transistors [para. 36], not the N-type transistors. In other words, Mojumder teach the left-side read buffer is made of P-type transistors, not N-type transistors (i.e., the fifth N-type transistor (N5) and the sixth N-type transistor (N6) as claimed).
Houston teaches an SRAM cell [Fig. 2] contains a pair of cross-coupled inverters (2002) which includes a bit-side data node (2004) and a bit-bar-side data node (2006). The SRAM cell (2000) further contains a first read buffer (2022) and a second read buffer (2024). The first read buffer (2022) includes a first access transistor (2026) and a first read buffer driver transistor (2028) that are depicted as NMOS transistors [para. 24-25]. Houston explains, “Each SRAM cell also contains two read buffers . . . “[E]ach read buffer may be independently formed with NMOS or PMOS transistors.” [para. 22]. Houston notes that the left side read buffer composed of access transistors 2025 and read buffer driver transistor 2028 are illustrated in Figure 2 as NMOS transistors, “but may be PMOS transistors” [para. 25]. In other words, Houston teaches that any read buffer may be made of PMOS transistors or NMOS transistors, at the discretion of those skilled in the art of SRAM.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Houston to the teachings of Mojumder et al. such that retaining one of Mojumder et al.’s read ports as PMOS read buffer while implementing the other read port of Mojumder et al. as Houston’s NMOS read buffer to achieve the predictable, routine design choice of mixed-polarity read paths and standard NMOS write access while preserving Mojumder et al.’s 10T SRAM architecture and read-sensing scheme.
Regarding claim 3, Mojumder et al. in combination with Houston teach the limitations with respect to claim 1.
Furthermore, Mojumder et al. disclose wherein
the third P-type transistor (P3) and the fourth P-type transistor (P4) are field effect transistors [the first read port 302 includes a PMOS transistor 304 (e.g., a pass gate) having a SiGe channel coupled to another PMOS transistor 306 having a SiGe channel, para. 35].
Houston discloses the fifth N-type transistor (N5) and the sixth N-type transistor (N6) are field effect transistors [The first access transistor (2026) and the first read buffer driver transistor (2028) are depicted in FIG. 2 as NMOS transistors, para. 25. The terms "driver transistor" and "access transistor" are understood to refer to a field effect transistor such as a metal oxide semiconductor (MOS) transistor, para. 15 and 17].
Regarding claim 4, Mojumder et al. in combination with Houston teach the limitations with respect to claim 1.
Furthermore, Mojumder et al. disclose wherein
the third P-type transistor (P3), the fourth P-type transistor (P4) are junction field effect transistors or metal oxide semiconductor field effect transistors [the first read port 302 includes a p-type metal oxide semiconductor (PMOS) transistor 304 (e.g., a pass gate) having a SiGe channel coupled to another PMOS transistor 306 having a SiGe channel, para. 4 as well as para. 35].
Houston discloses the fifth N-type transistor (N5), and the sixth N-type transistor (N6) are junction field effect transistors or metal oxide semiconductor field effect transistors [The first access transistor (2026) and the first read buffer driver transistor (2028) are depicted in FIG. 2 as NMOS transistors, para. 25. The terms "driver transistor" and "access transistor" are understood to refer to a field effect transistor such as a metal oxide semiconductor (MOS) transistor, para. 15 and 17].
Regarding claim 5, Mojumder et al. in combination with Houston teach the limitations with respect to claim 1.
Furthermore, Mojumder et al. disclose wherein
the first P-type transistor (P1) and the second P-type transistor (P2) are PMOS transistors [see Fig. 4, the write port 332 includes a PMOS transistor 408 (e.g., a pull-up transistor) having a SiGe channel and another PMOS transistor 410 (e.g., a pull-up transistor) having a SiGe channel, para. 40]; and
the first N-type transistor (N1), the second N-type transistor (N2), the third N-type transistor (N3), and the fourth N-type transistor (N4) are NMOS transistors [see Fig. 4, the write port 332 also includes an NMOS transistor 412 (e.g., a pull-down transistor), an NMOS transistor 414, an NMOS transistor 416 (e.g., a pass gate) and an NMOS transistor 418 (e.g., a pass gate), para. 40].
Regarding claim 6, Mojumder et al. in combination with Houston teach the limitations with respect to claim 1.
Furthermore, Mojumder et al. disclose wherein
the source terminal of the fourth P-type transistor (P4) is connected to the port C bit line [see Fig. 4, a source of the PMOS transistor 304 is coupled to a first read bit line (RBL1), para. 35], and the drain terminal of same is connected to the source terminal of the third P-type transistor (P3) [see Fig. 4, a source of the PMOS transistor 306 is coupled to a drain of the PMOS transistor 304, para. 35].
Houston discloses the source terminal of the sixth N-type transistor (N6) is connected to the drain terminal of the fifth N-type transistor (N5) [see Fig. 2, a second source/drain node of the first access transistor (2026) is connected to a drain node of the first read buffer driver transistor (2028), para. 25], and the drain terminal of same is connected to the port B bit line [see Fig. 2, a first source/drain node of the first access transistor (2026) is connected to a first read data line (2032), para. 25. The terms "bit line" and "bit-bar line" are understood to refer to data lines connected to passgate transistors or read buffers in a column of SRAM cells, para. 18].
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Mojumder et al. (20160064068) in view of Houston (US 20110044094) as applied to claim 1 above and further in view of Hsu et al. (US 20180366469).
Regarding claim 7, Mojumder et al. in combination with Houston teach the limitations with respect to claim 1.
However, Mojumder et al. in combination with Houston are silent with respect to wherein a chip layout structure thereof is as follows:
the first P-type transistor (P1) is located on the left side of the second P-type transistor (P2);
the first N-type transistor (N1) and the third N-type transistor (N3) are located on the left side of the first P-type transistor (P1), and the first N-type transistor (N1) is located on the front side of the third N-type transistor (N3);
the third P-type transistor (P3) and the fourth P-type transistor (P4) are located on the left side of the first N-type transistor (N1) and the third N-type transistor (N3), and the third P-type transistor (P3) is located on the front side of the fourth P-type transistor (P4);
the second N-type transistor (N2) and the fourth N-type transistor (N4) are located on the right side of the second P-type transistor (P2), and the second N-type transistor (N2) is located on the rear side of the fourth N-type transistor (N4); and
the fifth N-type transistor (N5) and the sixth N-type transistor (N6) are located on the right side of the second N-type transistor (N2) and the fourth N-type transistor (N4), and the fifth N-type transistor (N5) is located on the rear side of the sixth N-type transistor (N6).
Hsu et al. teach a chip layout structure [see Fig. 1B] thereof is as follows:
the first P-type transistor (P1) [Fig. 1B: Tr2] is located on the left side of the second P-type transistor (P2) [Fig. 1B: Tr3];
the first N-type transistor (N1) [Fig. 1B: Tr1] and the third N-type transistor (N3) [Fig. 1B: Tr7] are located on the left side of the first P-type transistor (P1) [see Fig. 1B: Tr2], and the first N-type transistor (N1) is located on the front side of the third N-type transistor (N3) [see Fig. 1B with respect to Fig. 1A].
the second N-type transistor (N2) [Fig. 1B: Tr4] and the fourth N-type transistor (N4) [Fig. 1B: Tr8] are located on the right side of the second P-type transistor (P2) [Fig. 1B: Tr3], and the second N-type transistor (N2) is located on the rear side of the fourth N-type transistor (N4) [see Fig. 1B with respect to Fig. 1A]; and
the fifth N-type transistor (N5) [Fig. 1B: Tr5] and the sixth N-type transistor (N6) [Fig. 1B: Tr6] are located on the right side of the second N-type transistor (N2) [Fig. 1B: Tr4] and the fourth N-type transistor (N4) [Fig. 1B: Tr8], and the fifth N-type transistor (N5) is located on the rear side of the sixth N-type transistor (N6) [see Fig. 1B with respect to Fig. 1A].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Hsu et al. to the teachings of Mojumder et al. in combination with Houston such that implementing the three-port SRAM of Mojumder et al. in combination with Houston using chip layout as taught by Hsu et al. to achieve the predictable use of known layout techniques to realize the known three-port SRAM function.
Regarding claim 8, Mojumder et al. in combination with Houston and Hsu et al. teach the limitations with respect to claim 7.
Furthermore, Hsu et al. disclose wherein the chip layout structure [Fig. 1B] thereof is as follows:
center lines of gate polysilicon of the first P-type transistor (P1), the first N-type transistor (N1), the third P-type transistor (P3), the fourth N-type transistor (N4), the sixth N-type transistor (N6) in the horizontal direction are on the same straight line [see Fig. 1B, the gates G1, G2, G3, G4, G5, G6, G7, and G8 are oriented lengthwise along the “x” direction with the gates G1, G2, G8, and G6 are aligned on a straight line, para. 30]; and
center lines of gate polysilicon of the second P-type transistor (P2), the third N-type transistor (N3), the fourth P-type transistor (P4), the second N-type transistor (N2), and the fifth N-type transistor (N5) in the horizontal direction are on the same straight line [see Fig. 1B, the gates G7, G3, G4, and the G5 are aligned on another straight line, para. 30].
Response to Arguments
Applicant's arguments filed with respect to independent claim 1 have been fully considered but they are not persuasive.
With respect to independent claim 1, Applicant first argues that “the doping type of the transistor in the first read port 302 (equivalent to port C) of Mojumder (20160064068) is the same as that of the transistor in the second read port 352 (equivalent to port B)”, see Applicant’s Remarks page 7. The Examiner agrees with that. Mojumder et al. describe first read port 302 including PMOS transistors 304-306 and second read port including PMOS transistors 354-356.
Applicant next argues that:
[T]the doping types of transistors in the first read buffer (2022) (equivalent to port C) and the second read buffer (2024) (equivalent to port B) shown in Figure 2 of Houston (US 20110044094) are the same. Houston only notes that “The first read buffer (2022) includes a first access transistor (2026) and a first read buffer driver transistor (2028). The first access transistor (2026) and the first read buffer driver transistor (2028) are depicted in FIG. 2 as NMOS transistors, but may be PMOS transistors in other embodiments". However, Houston did not disclose that the doping type of the transistor in the first read buffer (2022) (equivalent to port C) is the same as that in the second read buffer (2024) (equivalent to port B). So, Houston did not provide any inspiration into the distinguishing technical feature “the doping type of the transistor in port C is opposite to that in port B.
see Applicant’s Remarks page 7.
This particular remark is not considered persuasive because it attacks Houston’s Figure 2 embodiment in isolation, whereas the rejection is based on the combined teachings of Mojumder et al. and Houston. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references [see MPEP 2145 IV].
More importantly, Houston also teaches that each read buffer may be independently formed with NMOS or PMOS transistors [para. 22]. Houston further discloses in Figure 2 the first read buffer (2022) includes a first access transistor (2026) and a first read buffer driver transistor (2028) and the second read buffer (2024) is configured similarly to the first read buffer (2022). The first access transistor (2026) and the first read buffer driver transistor (2028) are depicted in FIG. 2 as NMOS transistors, but may be PMOS transistors in other embodiments [para. 25]. After that, Houston discloses in Figure 10 a circuit diagram of a part of an SRAM cell containing a read buffer with PMOS passgate transistors instead of NMOS passgate transistors with appropriate changes in polarity [para. 51]. Thus, Houston provides an express teaching that read buffer polarity is independently selectable on a per buffer basis and the same two transistors read buffer topology can be implemented in either doping type. A person having ordinary skill in the art before the effective filling date of the claimed invention would have found it obvious to apply the teachings of Houston to the teachings of Mojumder et al. such that retaining one of Mojumder et al.’s read ports as PMOS read buffer while implementing the other read port of Mojumder et al. as Houston’s NMOS read buffer to achieve the predictable, routine design choice of mixed-polarity read paths and standard NMOS write access while preserving Mojumder et al.’s 10T SRAM architecture and read-sensing scheme.
Lastly, applicant argues that:
[I]n the three-port SRAM circuit of the present application, storage states of the first node n1 and the second node n2 of a six-transistor single-port (6T SP) SRAM circuit are opposite, so that the third P-type transistor P3 with the gate terminal thereof corresponding to the first node n1 and the fifth N-type transistor N5 with the gate terminal thereof corresponding to the second node n2 can be on/off synchronously. When the system is in a read state, that is, when the sixth N-type transistor N6 and the fourth P-type transistor P4 are both on, the port C bit line C-BL and the port B bit line B-BL can be held/discharge synchronously, so as to facilitate the system operating the peripheral circuit simultaneously when reading ports B and C at high speeds. The system can operate the peripheral circuit without the use of an inverter for determining a storage state. The three port SRAM circuit of this patent application can solve technical problems that neither Mojumder nor Houston can solve and achieve beneficial technical effects.”
see Applicant’s Remarks page 7.
This particular remark is also not considered persuasive for at least two reasons. First, claim 1 does not recite a limitation requiring synchronous hold/discharge behavior, simultaneous peripheral operation, or the absence of an inverter. During prosecution, claims are given their broadest reasonable interpretation, and features described in the Specification but not positively recited in the claim are not imported into the claim. Second, the asserted operational effect would not have been unexpected on this record. Houston teaches concurrent read operations through dual read buffers without risking data upsets [para. 29] and Mojumder et al. teach that multiple read ports enable enhanced single ended read operations and improved read performance. Houston also teaches connecting the first and second read buffer driver gates to opposite gate nodes. Thus, once one read port is implemented in PMOS form and the other in NMOS form on opposite nodes of a cross coupled latch, the asserted read behavior would have been at least a predictable consequence of the known cell topology rather than persuasive evidence of nonobviousness.
For the above reasons, the applied rejection is considered proper and maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825