DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Invention I drawn to a device claims 1-7, in the reply filed on 08/14/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. TW 113118232, filed on 07/15/2024.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 06/16/2024 is/are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Response to Amendment
The amendment with respect to claim(s) filed on 9/9/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 1-7 have been considered. The non-elected Claims 8-20 are withdrawn by the Applicant.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Da Chen, (hereinafter CHEN), CN 109003936 B, in view of Srinath Krishnan et al, (hereinafter KRISHNAN), US 6613643 B1.
Regarding Claim 1, CHEN teaches a semiconductor structure (Fig. 8, semiconductor device, [0060]) comprising a silicon-on-insulator substrate (Fig. 5, S21, SOI substrate, [0085]), comprising:
a material layer (Fig. 8, 101, first silicon layer) defined with a central region (annotated Figure 8) and two edge regions (annotated Figure 8), wherein the central region is situated between the two edge regions (annotated Figure 8);
an oxide layer (Fig. 8, 103) and a silicon layer (Fig. 8, 112/122, third silicon layer/embedded silicon layer) stacked from bottom to top (annotated Figure 8) on the material layer (Fig. 8, 101, first silicon layer), wherein a thickness of the silicon layer (Fig. 8, 112/122, third silicon layer/embedded silicon layer) in the central region greater (annotated Figure 8) than a thickness of the silicon layer (Fig. 8, 112/122, third silicon layer/embedded silicon layer) in the two edge regions (annotated Figure 8).
Though CHEN teaches a semiconductor structure comprising a silicon-on-insulator substrate, comprising: a thickness of the two silicon layers combined in the central region greater than a thickness of the silicon layer in the two edge regions, CHEN does not explicitly disclose a semiconductor structure comprising a silicon-on-insulator substrate, comprising: a thickness of the silicon layer in the central region greater than a thickness of the silicon layer in the two edge regions.
PNG
media_image1.png
832
1168
media_image1.png
Greyscale
KRISHNAN teaches a semiconductor structure (Fig. 1, 10, structure) comprising a silicon-on-insulator substrate (Fig. 8, 32, SOI substrate), comprising: a thickness of the silicon layer (Fig. 8, 34, silicon device layer) in the central region greater (annotated Figure 8) than a thickness (Fig. 8, 34, silicon device layer) of the silicon layer in the two edge regions (annotated Figure 8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified CHEN to incorporate the teachings of KRISHNAN, such that a semiconductor structure comprising a silicon-on-insulator substrate, comprising: a thickness of the silicon layer in the central region greater than a thickness of the silicon layer in the two edge regions, so that the SOI device can have advantages include: reduced source/drain capacitance, and hence improved speed performance at higher-operating frequencies and lower voltage applications (KRISHNAN, [Col. 1, Lines, 30-45]).
PNG
media_image2.png
704
1195
media_image2.png
Greyscale
Regarding Claim 2, CHEN as modified by KRISHNAN teaches the semiconductor structure according to claim 1.
CHEN further teaches the semiconductor structure (Fig. 8, semiconductor device, [0060]), wherein the oxide layer (Fig. 8, 103) in the two edge regions (annotated Figure 8) has mutually aligned top surfaces (annotated Figure 8).
PNG
media_image3.png
832
1168
media_image3.png
Greyscale
Regarding Claim 3, CHEN as modified by KRISHNAN teaches the semiconductor structure according to claim 1.
KRISHNAN further teaches the semiconductor structure (Fig. 1, 10, structure), wherein a bottom surface of the silicon layer (Fig. 8, 34, silicon device layer) in the central region (annotated Figure 8) is lower than a bottom surface of the silicon layer (Fig. 8, 34, silicon device layer) in the two edge regions (annotated Figure 8).
PNG
media_image4.png
731
1213
media_image4.png
Greyscale
Regarding Claim 4, CHEN as modified by KRISHNAN teaches the semiconductor structure according to claim 1.
CHEN further teaches the semiconductor structure (Fig. 8, semiconductor device, [0060]), further comprising a gate structure (Fig. 8, 109, polysilicon gate) located on the silicon layer (Fig. 8, 112/122, third silicon layer/embedded silicon layer) and situated within the central region (annotated Figure 8).
PNG
media_image5.png
832
1168
media_image5.png
Greyscale
Regarding Claim 5, CHEN as modified by KRISHNAN teaches the semiconductor structure according to claim 1.
CHEN further teaches the semiconductor structure (Fig. 8, semiconductor device, [0060]), further comprising a source region (Fig. 8, 105) and a drain region (Fig. 8, 115) located within the silicon layer (Fig. 8, 112/122, third silicon layer/embedded silicon layer) and respectively positioned within the two edge regions (annotated Figure 8).
PNG
media_image6.png
832
1168
media_image6.png
Greyscale
Regarding Claim 6, CHEN as modified by KRISHNAN teaches the semiconductor structure according to claim 1.
CHEN further teaches the semiconductor structure (Fig. 8, semiconductor device, [0060]), further comprising shallow trench isolation (Fig. 8, 104) located on the oxide layer (Fig. 8, 103) and positioned on both sides of the silicon layer (Fig. 8, 112/122, third silicon layer/embedded silicon layer).
Regarding Claim 7, CHEN as modified by KRISHNAN teaches the semiconductor structure according to claim 1.
CHEN further teaches the semiconductor structure (Fig. 8, semiconductor device, [0060]), wherein a top surface (annotated Figure 8) of the silicon layer (Fig. 8, 112/122, third silicon layer/embedded silicon layer) is aligned with a top surface (annotated Figure 8) of the shallow trench isolation (Fig. 8, 104).
PNG
media_image7.png
832
1168
media_image7.png
Greyscale
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 6441435 B1 – Figure 10
STATEMENT OF RELEVANCE – The semiconductor substrate (16) made of silicon, the insulator layer (20) made of silicon oxide, and the surface semiconductor layer (18), made of silicon are stacked from bottom to top wherein the gate structure (22) is formed on top of the surface semiconductor layer (18).
CN 108682649 A - Figure 5(B)
STATEMENT OF RELEVANCE – A silicon layer (401), an oxide layer (402), and the silicon layer (303) are stacked from bottom to top wherein the polysilicon gate (502) is formed on top of the silicon layer (303).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SESHA SAIRAMAN SRINIVASAN/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights