DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-6, 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simsek-Ege (US 2022/0375930) in view of Ikeda et al. (US 2012/0176834 “Ikeda”).
Regarding claim 1, Simsek-Ege discloses a memory device, comprising:
a plurality of memory arrays (arrays 110-a; fig. 3) stacked one over another (“multiple memory arrays 110 arranged in a stack of decks or levels” para 0027) along a thickness direction (Z axis; fig. 3) of the memory device, wherein each of the plurality of memory arrays (arrays 110-a detailed as arrays 110; fig. 1) comprises:
a first bit line (i.e. digit lines 130; fig. 1), and
at least one memory cell (105; fig. 1) coupled to the first bit line (“each column of memory cells 105 may be coupled with one or more digit lines 130” para 0017), and
the first bit lines of at least two memory arrays among the plurality of memory arrays are electrically coupled to each other (“an interconnection region 370-b-1 that couples digit lines of decks 315-a-1 and 315-a-2” and “an interconnection region 370-b-2 that includes interconnects that couple digit lines of decks 315-a-3 and 315-a-4” para 0054),
the memory further comprises:
a first via structure (interconnection region 370-b-1 functions as a via structure; fig. 3 para 0052) extending along the thickness direction (Z axis), and electrically coupling the first bit lines of a first set of memory arrays (i.e. “digit lines of decks 315-a-1 and 315-a-2”) among the plurality of memory arrays to each other (fig. 3 para 0052); and
a second via structure (interconnection region 370-b-2 functions as a via structure; fig. 3 para 0052) extending along the thickness direction (Z axis), and electrically coupling the first bit lines of a second set of memory arrays (i.e. “digit lines of decks 315-a-3 and 315-a-4”) among the plurality of memory arrays to each other (fig. 3 para 0052).
Simsek-Ege does not expressly disclose wherein the first set of memory arrays and the second set of memory arrays share a common memory array.
Ikeda discloses wherein the first set of memory arrays (top array in the Z axis; fig. 14A) and the second set of memory arrays (middle array in the Z axis; fig. 14A) share a common memory array (the top and middle array is commonly coupled to a bottom array in the Z axis; fig. 14A).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Ikeda for the purpose of achieving an improved device with different layout of various elements as arranged in an integrated system (para 0147 of Ikeda), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Regarding claim 2, Simsek-Ege discloses the memory device of claim 1, wherein the first bit lines of all of the plurality of memory arrays (i.e. all plurality of memory arrays respective to each set 310-a, 310-b; fig. 3) are electrically coupled to each other (para 0053).
Regarding claim 4, Ikeda discloses the memory device of claim 2, further comprising:, and the first bit line (Bit line BL; fig. 14A) of the common memory array is between and couples the first via structure (162/163; fig. 14A, 14B) and the second via structure (151/161 or lower first/second vias; fig. 14A, 14B), to electrically couple the first bit lines (BL_e, BLo; fig. 14A, 14B) of all of the plurality of memory arrays (i.e. of memory levels; fig. 14A, 14B) to each other.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Ikeda for the purpose of achieving an improved device with different layout of various elements as arranged in an integrated system (para 0147 of Ikeda), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Regarding claim 5, Simsek-Ege disclose memory device of claim 4, wherein the first via structure and the second via structure overlap each other along the thickness direction (fig. 3).
Regarding claim 6, Ikeda discloses the memory device of claim 4, wherein the first via structure and the second via structure do not overlap each other along the thickness direction (fig. 14A, 14B).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Ikeda for the purpose of achieving an improved device with different layout of various elements as arranged in an integrated system (para 0147 of Ikeda), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Regarding claim 21, Ikeda discloses the memory device of claim 1, wherein along the thickness direction, the first bit line of the common memory array is physically between the first via structure and the second via structure, and the first bit line of the common memory array electrically couples the first via structure to the second via structure (fig. 14A, further detailed fig. 6).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Ikeda for the purpose of achieving an improved device with different layout of various elements as arranged in an integrated system (para 0147 of Ikeda), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simsek-Ege (US 2022/0375930) in view of Ikeda et al. (US 2012/0176834 “Ikeda”), and further in view of Kan et al. (US 2018/0061467 “Kan”).
Regarding claim 8, Simsek-Ege does not expressly disclose the memory device of claim 1, wherein the at least one memory cell in at least one of the plurality of memory arrays has a first memory cell configuration which comprises: a magnetic tunnel junction (MTJ) structure, a spin-orbit torque (SOT) layer in contact with the MTJ structure, a first selector coupled in series with the SOT layer, between the first bit line and a write word line, and a second selector coupled between the MTJ structure and a read word line.
Kan discloses a magnetic tunnel junction (MTJ) structure (610; fig. 6), a spin-orbit torque (SOT) layer (620; fig. 6) in contact with the MTJ structure, a first selector (610; fig. 6) coupled in series with the SOT layer, between the first bit line (BL; fig. 6) and a write word line (WWL; fig. 6), and a second selector (640; fig. 6) coupled between the MTJ structure (610) and a read word line (RWL; fig. 6).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Kan for the purpose of facilitating data accessing schemes by improving the endurance and the lifetime of the memory, which is common and well known in the art to secure the integrity of data storage (para 0051 of Kan).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simsek-Ege (US 2022/0375930) in view of Ikeda et al. (US 2012/0176834 “Ikeda”), in view of Kan et al. (US 2018/0061467 “Kan”), and further in view of Lin et al. (US 2006/0038210 “Lin”).
Regarding claim 9, Simsek-Ege discloses the memory device of claim 8, wherein the at least one memory cell in each of the plurality of memory arrays, a layer in a first memory array among the plurality of memory arrays is different from a layer in a second memory array among the plurality of memory arrays (i.e. different memory architectures; para 0042).
Simsek-Ege as modified, does not expressly disclose has the first memory cell configuration in which the MTJ structure comprises a tunnel barrier layer, and a thickness of the tunnel barrier layer in a first memory is different from a thickness of the tunnel barrier layer in a second memory.
Lin discloses has the first memory cell configuration in which the MTJ structure comprises a tunnel barrier layer, and a thickness of the tunnel barrier layer in a first memory is different from a thickness of the tunnel barrier layer in a second memory (tunnel barrier of different MTJ devices having a different thickness; para 0006).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is further modifiable as taught by Lin for the purpose of achieving an improved device with different memory technologies of various memories as arranged in an integrated system (para 0058 of Lin), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Claim(s) 10, 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simsek-Ege (US 2022/0375930) in view of Ikeda et al. (US 2012/0176834 “Ikeda”), and further in view of Mauri et al. (US 2021/0055360 “Mauri”).
Regarding claim 10, Simsek-Ege does not expressly disclose the memory device of claim 1, wherein different memory arrays among the plurality of memory arrays have different resistance- area products.
Mauri discloses wherein different memory arrays (each magnetoresistance leg having a different array; para 0073) among the plurality of memory arrays have different resistance-area products (“The leg with positive polarity was formed by depositing a Film B and the leg with negative polarity was formed by depositing a Film A on the same wafer substrate in which Film A and Film B had different resistance area (RA) products” para 0073).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Mauri for the purpose of achieving different memory technologies of various arrays as arranged in an integrated system (para 0053 of Mauri), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Regarding claim 22, Mauri discloses the memory device of claim 10, wherein the different resistance-area products (RA products) are different from each other by integer multiples of a predetermined number (a sampled magnetic field has integer multiples of a predetermined number 200, i.e. -600, -400, -200, 0, 200, 400, 600; further, at each integer multiple the measure RA product is different; fig. 11A).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Mauri for the purpose of achieving different memory technologies of various arrays as arranged in an integrated system (para 0053 of Mauri), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Claim(s) 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simsek-Ege (US 2022/0375930) in view of Mauri et al. (US 2021/0055360 “Mauri”).
Regarding claim 11, Simsek-Ege discloses a memory device, comprising:
circuitry over a substrate (para 0027); and
a plurality of memory arrays (arrays 110-a; fig. 3) stacked (“multiple memory arrays 110 arranged in a stack of decks or levels” para 0027) along a thickness direction (Z axis; fig. 3) of the substrate over the circuitry and the substrate (para 0027), wherein at least two of the plurality of memory arrays are connected (“an interconnection region 370-b-1 that couples digit lines of decks 315-a-1 and 315-a-2” and “an interconnection region 370-b-2 that includes interconnects that couple digit lines of decks 315-a-3 and 315-a-4” para 0053) by at least one via (370-b-1, 370-b-2).
Simsek-Ege does not expressly disclose different memory arrays among the plurality of memory arrays have different resistance-area products, and the different resistance-area products are different from each other by integer multiples of a predetermined number.
Mauri discloses different memory arrays (each magnetoresistance leg having a different array; para 0073) among the plurality of memory arrays have different resistance-area products (“The leg with positive polarity was formed by depositing a Film B and the leg with negative polarity was formed by depositing a Film A on the same wafer substrate in which Film A and Film B had different resistance area (RA) products” para 0073), and the different resistance-area products (RA products) are different from each other by integer multiples of a predetermined number (a sampled magnetic field has integer multiples of a predetermined number 200, i.e. -600, -400, -200, 0, 200, 400, 600; further, at each integer multiple the measure RA product is different; fig. 11A).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Mauri for the purpose of achieving different memory technologies of various arrays as arranged in an integrated system (para 0053 of Mauri), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Regarding claim 12, Mauri disclose the memory device of claim 11, wherein at least two memory arrays among the plurality of memory arrays comprise memory cells of different memory technologies (para 0073).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Mauri for the purpose of achieving different memory technologies of various arrays as arranged in an integrated system (para 0053 of Mauri), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Regarding claim 13, Simsek-Ege discloses the memory device of claim 12, wherein the different memory technologies (i.e. different memory architectures; para 0042) comprise at least two selected from the group consisting of: spin-orbit torque (SOT) magnetoresistive random-access memory (MRAM),spin-transfer torque (STT) MRAM, resistive RAM (RRAM) (para 0042),phase-change memory (PCM) (para 0042),ferroelectric RAM (FeRAM) (para 0042), and electrochemical RAM (ECRAM).
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simsek-Ege (US 2022/0375930) in view of Mauri et al. (US 2021/0055360 “Mauri”), and further in view of Lin et al. (US 2006/0038210 “Lin”).
Regarding claim 14, Simsek-Ege as modified, does not expressly disclose the memory device of claim 11, wherein the different memory arrays having the different resistance-area products comprise memory cells of a same memory technology, and include correspondingly different thicknesses of a layer which is configured to pass therethrough a current in an operation of the memory device.
Mauri discloses the different memory arrays having the different resistance-area products comprise memory cells of a same memory technology (i.e. the memory cells are of magnetoresistive memory technology; para 0026).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Mauri for the purpose of achieving different memory technologies of various arrays as arranged in an integrated system (para 0053 of Mauri), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Lin discloses include correspondingly different thicknesses of a layer (tunnel barrier of different MTJ devices having a different thickness; para 0006) which is configured to pass therethrough a current in an operation of the memory device (para 0052-0053) or a CIM operation.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is further modifiable as taught by Lin for the purpose of achieving an improved device with different memory technologies of various memories as arranged in an integrated system (para 0058 of Lin), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Regarding claim 15, Mauri discloses the memory device of claim 11, the different memory arrays having the different resistance-area products (para 0073).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Mauri for the purpose of achieving different memory technologies of various arrays as arranged in an integrated system (para 0053 of Mauri), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Lin discloses wherein the memory technology is magnetoresistive random-access memory (MRAM) (fig. 13), the layer is a tunnel barrier layer, and the different memory include correspondingly different thicknesses of the tunnel barrier layer (para 0006).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is further modifiable as taught by Lin for the purpose of achieving an improved device with different memory technologies of various memories as arranged in an integrated system (para 0058 of Lin), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Allowable Subject Matter
Claim(s) 23 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 23, the prior art fails to teach or suggest the claimed limitations, namely a first memory array with a lowest resistance-area product is configured to store most significant bit (MSB) data of the first data, and a second memory array with a highest resistance-area product is configured to store least significant bit (LSB) data of the first data.
The allowable claims are supported in at least paragraph 0058 of the instant application.
Response to Arguments
Applicant's arguments filed 8/24/26 have been fully considered but are not persuasive.
The applicant submits that Ikeda et al. (US 2021/0176834 “Ikeda”) fails to disclose first and second memory arrays sharing a common array (on page 11 of the response, regarding the pending claim(s)).
The examiner respectfully disagrees with the arguments. MPEP § 2111 discusses proper claim interpretation, including giving claims their broadest reasonable interpretation in light of the specification during examination. Under broadest reasonable interpretation (BRI), the words of a claim must be given their plain meaning unless such meaning is inconsistent with the specification, and it is improper to import claim limitations from the specification into the claim.
The BRI of claim 1, directed to the limitation share a common array as argued, can be interpreted as including multiple common elements and ways to share. Applicant’s annotated fig. 14 is incorrect regarding the referenced elements of the previous Office Action, as the sets of arrays shown in Ikeda comprises a top, middle, and bottom sets of arrays (i.e. each array of memory cells), and not merely defined as the bit lines coupled thereto (page 12 of the response). That is, Ikeda discloses an upper set of memory arrays and a middle set of memory arrays, i.e. first set and second set of memory arrays, coupled to bit line BL_e0 (fig. 14A). A conductive through via 162 electrically couples BL_e0 to a bottom bit line BL of a bottom set of arrays. As such, all the arrays are electrically coupled through shared interconnections and electrical communications, i.e. any of the aforementioned array is therefore considered a common array, including the bottom set of arrays.
Furthermore, a person of ordinary skill is also a person of ordinary creativity, not an automaton, and in many cases will be able to fit teachings of multiple patents together like pieces of a puzzle (See MPEP § 2141.03). Given this creativity the ability to fit teachings of multiple patents together like the pieces of a puzzle, one of ordinary skill in the art would be able to combine the teachings in such a way to reflect the shared common array as required by the claim, as there are more ways than those submitted by applicant. Therefore, the bottom “common” set of arrays of Ikeda is considered to meet the BRI of “the first set of memory arrays and the second set of memory arrays share a common memory array.”
Regarding claim 11, applicant submits that Mauri et al. (US 2021/0055360 “Mauri”) fails to disclose integer multiples. However, Mauri discloses that the different resistance-area products are measured at different integer multiples of a magnetic field, as graphically represented (fig. 11A).
Regarding non-elected claim 17 (Group IV is the previous restriction requirement), the claim directs to a memory device that does not overlap in scope with examined Groups I-III, as the groups are not obvious variants and considered distinct from each other.
For at least the aforementioned reasons, the rejection is deemed proper and made final.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/UYEN SMET/
Primary Examiner, Art Unit 2824______
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