DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election with traverse of Group I (claims 1-7 and 9-10) in the reply filed on 1/13/2026 is acknowledged.
It is found persuasive with Group II (claim 8) and Group III (claims 11-16). In light of the traversal, the restriction requirement regarding Group II and Group III is withdrawn, and claims 1-16 are examined together. It is not found persuasive with Group IV (claims 17-20). Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Further, the inventions are distinct and restriction is proper because reasons exist for insisting upon the restriction, i.e., there would be a serious search burden as evidenced by separate classification, status, or field of search and/or a serious examination burden as evidenced by, for example, non-prior art issues relevant to one invention that are not relevant to the other invention because the groups are not obvious variants of each other. That is, Group IV does not overlap in scope with Groups I-III.
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2018/0130519 “Chen”).
Regarding claim 1, Chen discloses a memory device, comprising:
a plurality of memory arrays (“two memory array layers 102, 104 are shown, but the 3D SRAM structure 100 may include additional memory array layers” para 0015) stacked one over another (“memory array layers 102, 104 vertically disposed one above another” para 0015) along a thickness direction (3rd AXIS; fig. 2) of the memory device, wherein each of the plurality of memory arrays comprises:
a first bit line (128, 129; fig. 2), and
at least one memory cell (106; fig. 2) coupled to the first bit line (“each memory cell [106] in a memory array layer [102, 104] has a unique bit line pair [128,129] to which it can couple” para 0024), and
the first bit lines of at least two memory arrays among the plurality of memory arrays are electrically coupled to each other (“each memory cell in a memory array layer has a unique bit line pair to which it can couple and those bit line pairs couple to a single memory cell in each additional memory array layer” para 0024, further “a first bit line coupled to a single memory cell in the first memory array layer and a single memory cell in the second memory array layer” claim 1).
Regarding claim 2, Chen discloses the memory device of claim 1, wherein the first bit lines of all of the plurality of memory arrays are electrically coupled to each other (“each memory cell in a memory array layer has a unique bit line pair to which it can couple and those bit line pairs couple to a single memory cell in each additional memory array layer” para 0024).
Claim(s) 1-3, 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Simsek-Ege (US 2022/0375930).
Regarding claim 1, Simsek-Ege discloses a memory device, comprising:
a plurality of memory arrays (arrays 110-a; fig. 3) stacked one over another (“multiple memory arrays 110 arranged in a stack of decks or levels” para 0027) along a thickness direction (Z axis; fig. 3) of the memory device, wherein each of the plurality of memory arrays (arrays 110-a detailed as arrays 110; fig. 1) comprises:
a first bit line (i.e. digit lines 130; fig. 1), and
at least one memory cell (105; fig. 1) coupled to the first bit line (“each column of memory cells 105 may be coupled with one or more digit lines 130” para 0017), and
the first bit lines of at least two memory arrays among the plurality of memory arrays are electrically coupled to each other (“an interconnection region 370-b-1 that couples digit lines of decks 315-a-1 and 315-a-2” and “an interconnection region 370-b-2 that includes interconnects that couple digit lines of decks 315-a-3 and 315-a-4” para 0053).
Regarding claim 2, Simsek-Ege discloses the memory device of claim 1, wherein the first bit lines of all of the plurality of memory arrays (i.e. all plurality of memory arrays respective to each set 310-a, 310-b; fig. 3) are electrically coupled to each other (para 0053).
Regarding claim 3, Simsek-Ege discloses the memory device of claim 2, further comprising: a via structure (370-b-1, 370-b-2; fig. 3) extending along the thickness direction, and electrically coupling the first bit lines of all of the plurality of memory arrays to each other (para 0053).
Regarding claim 7, Simsek-Ege discloses the memory device of claim 1, wherein the plurality of memory arrays comprises at least two further memory arrays other than the at least two memory arrays (i.e. plurality of memory arrays respective to each set 310-a, 310-b; fig. 3), and the first bit lines of at least two further memory arrays are electrically coupled to each other, without being electrically coupled to the first bit lines of at least two memory arrays (para 0053).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simsek-Ege (US 2022/0375930) in view of Ikeda et al. (US 2012/0176834 “Ikeda”).
Regarding claim 4, Simsek-Ege discloses the memory device of claim 2, further comprising: a first via structure extending along the thickness direction (370-b-1; fig. 3), and electrically coupling the first bit lines of a first set of memory arrays among the plurality of memory arrays to each other; and a second via structure (370-b-2; fig. 3) extending along the thickness direction, and electrically coupling the first bit lines of a second set of memory arrays among the plurality of memory arrays to each other.
Simsek-Ege does not expressly disclose wherein the first set of memory arrays and the second set of memory arrays share a common memory array, and the first bit line of the common memory array is between and couples the first via structure and the second via structure, to electrically couple the first bit lines of all of the plurality of memory arrays to each other.
Ikeda discloses wherein the first set of memory arrays and the second set of memory arrays share a common memory array, and the first bit line (Bit line BL; fig. 14A) of the common memory array is between and couples the first via structure (162/163; fig. 14A, 14B) and the second via structure (151/161 or lower first/second vias; fig. 14A, 14B), to electrically couple the first bit lines (BL_e, BLo; fig. 14A, 14B) of all of the plurality of memory arrays (i.e. of memory levels; fig. 14A, 14B) to each other.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Ikeda for the purpose of achieving an improved device with different layout of various elements as arranged in an integrated system (para 0147 of Ikeda), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Regarding claim 5, Simsek-Ege disclose memory device of claim 4, wherein the first via structure and the second via structure overlap each other along the thickness direction (fig. 3).
Regarding claim 6, Ikeda discloses the memory device of claim 4, wherein the first via structure and the second via structure do not overlap each other along the thickness direction (fig. 14A, 14B).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Ikeda for the purpose of achieving an improved device with different layout of various elements as arranged in an integrated system (para 0147 of Ikeda), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simsek-Ege (US 2022/0375930) in view of Kan et al. (US 2018/0061467 “Kan”).
Regarding claim 8, Simsek-Ege does not expressly disclose the memory device of claim 1, wherein the at least one memory cell in at least one of the plurality of memory arrays has a first memory cell configuration which comprises: a magnetic tunnel junction (MTJ) structure, a spin-orbit torque (SOT) layer in contact with the MTJ structure, a first selector coupled in series with the SOT layer, between the first bit line and a write word line, and a second selector coupled between the MTJ structure and a read word line.
Kan discloses a magnetic tunnel junction (MTJ) structure (610; fig. 6), a spin-orbit torque (SOT) layer (620; fig. 6) in contact with the MTJ structure, a first selector (610; fig. 6) coupled in series with the SOT layer, between the first bit line (BL; fig. 6) and a write word line (WWL; fig. 6), and a second selector (640; fig. 6) coupled between the MTJ structure (610) and a read word line (RWL; fig. 6).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Kan for the purpose of facilitating data accessing schemes by improving the endurance and the lifetime of the memory, which is common and well known in the art to secure the integrity of data storage (para 0051 of Kan).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simsek-Ege (US 2022/0375930) in view of Kan et al. (US 2018/0061467 “Kan”), and further in view of Lin et al. (US 2006/0038210 “Lin”).
Regarding claim 9, Simsek-Ege discloses the memory device of claim 8, wherein the at least one memory cell in each of the plurality of memory arrays, a layer in a first memory array among the plurality of memory arrays is different from a layer in a second memory array among the plurality of memory arrays (i.e. different memory architectures; para 0042).
Simsek-Ege as modified, does not expressly disclose has the first memory cell configuration in which the MTJ structure comprises a tunnel barrier layer, and a thickness of the tunnel barrier layer in a first memory is different from a thickness of the tunnel barrier layer in a second memory.
Lin discloses has the first memory cell configuration in which the MTJ structure comprises a tunnel barrier layer, and a thickness of the tunnel barrier layer in a first memory is different from a thickness of the tunnel barrier layer in a second memory (tunnel barrier of different MTJ devices having a different thickness; para 0006).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is further modifiable as taught by Lin for the purpose of achieving an improved device with different memory technologies of various memories as arranged in an integrated system (para 0058 of Lin), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Claim(s) 10-13, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simsek-Ege (US 2022/0375930) in view of Mauri et al. (US 2021/0055360 “Mauri”).
Regarding claim 10, Simsek-Ege does not expressly disclose the memory device of claim 1, wherein different memory arrays among the plurality of memory arrays have different resistance- area products.
Mauri discloses wherein different memory arrays (each magnetoresistance leg having a different array; para 0073) among the plurality of memory arrays have different resistance-area products (“The leg with positive polarity was formed by depositing a Film B and the leg with negative polarity was formed by depositing a Film A on the same wafer substrate in which Film A and Film B had different resistance area (RA) products” para 0073).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Mauri for the purpose of achieving different memory technologies of various arrays as arranged in an integrated system (para 0053 of Mauri), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Regarding claim 11, Simsek-Ege discloses a memory device, comprising:
circuitry over a substrate (para 0027); and
a plurality of memory arrays (arrays 110-a; fig. 3) stacked (“multiple memory arrays 110 arranged in a stack of decks or levels” para 0027) along a thickness direction (Z axis; fig. 3) of the substrate over the circuitry and the substrate (para 0027), wherein at least two of the plurality of memory arrays are connected (“an interconnection region 370-b-1 that couples digit lines of decks 315-a-1 and 315-a-2” and “an interconnection region 370-b-2 that includes interconnects that couple digit lines of decks 315-a-3 and 315-a-4” para 0053) by at least one via (370-b-1, 370-b-2).
Simsek-Ege does not expressly disclose different memory arrays among the plurality of memory arrays have different resistance-area products.
Mauri discloses different memory arrays (each magnetoresistance leg having a different array; para 0073) among the plurality of memory arrays have different resistance-area products (“The leg with positive polarity was formed by depositing a Film B and the leg with negative polarity was formed by depositing a Film A on the same wafer substrate in which Film A and Film B had different resistance area (RA) products” para 0073).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Mauri for the purpose of achieving different memory technologies of various arrays as arranged in an integrated system (para 0053 of Mauri), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Regarding claim 12, Mauri disclose the memory device of claim 11, wherein at least two memory arrays among the plurality of memory arrays comprise memory cells of different memory technologies (para 0073).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Mauri for the purpose of achieving different memory technologies of various arrays as arranged in an integrated system (para 0053 of Mauri), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Regarding claim 13, Simsek-Ege discloses the memory device of claim 12, wherein the different memory technologies (i.e. different memory architectures; para 0042) comprise at least two selected from the group consisting of: spin-orbit torque (SOT) magnetoresistive random-access memory (MRAM),spin-transfer torque (STT) MRAM, resistive RAM (RRAM) (para 0042),phase-change memory (PCM) (para 0042),ferroelectric RAM (FeRAM) (para 0042), and electrochemical RAM (ECRAM).
Regarding claim 16, Mauri disclose the memory device of claim 11, wherein the different resistance-area products are different from each other by multiples of a predetermined number (fig. 11A-11C).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Mauri for the purpose of achieving different memory technologies of various arrays as arranged in an integrated system (para 0053 of Mauri), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simsek-Ege (US 2022/0375930) in view of Mauri et al. (US 2021/0055360 “Mauri”), and further in view of Lin et al. (US 2006/0038210 “Lin”).
Regarding claim 14, Simsek-Ege as modified, does not expressly disclose the memory device of claim 11, wherein the different memory arrays having the different resistance-area products comprise memory cells of a same memory technology, and include correspondingly different thicknesses of a layer which is configured to pass therethrough a current in a read operation or a CIM operation.
Mauri discloses the different memory arrays having the different resistance-area products comprise memory cells of a same memory technology (i.e. the memory cells are of magnetoresistive memory technology; para 0026).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Mauri for the purpose of achieving different memory technologies of various arrays as arranged in an integrated system (para 0053 of Mauri), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Lin discloses include correspondingly different thicknesses of a layer (tunnel barrier of different MTJ devices having a different thickness; para 0006) which is configured to pass therethrough a current in a read operation (para 0052-0053) or a CIM operation.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is further modifiable as taught by Lin for the purpose of achieving an improved device with different memory technologies of various memories as arranged in an integrated system (para 0058 of Lin), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Regarding claim 15, Mauri discloses the memory device of claim 11, the different memory arrays having the different resistance-area products (para 0073).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is modifiable as taught by Mauri for the purpose of achieving different memory technologies of various arrays as arranged in an integrated system (para 0053 of Mauri), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Lin discloses wherein the memory technology is magnetoresistive random-access memory (MRAM) (fig. 13), the layer is a tunnel barrier layer, and the different memory include correspondingly different thicknesses of the tunnel barrier layer (para 0006).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Simsek-Ege is further modifiable as taught by Lin for the purpose of achieving an improved device with different memory technologies of various memories as arranged in an integrated system (para 0058 of Lin), which is reasonably expected because one of ordinary skill in the art would recognize that having a device with different arrangements for utility will allow for more flexibility in combination within the system, such as the integrated multi-deck system of Simsek-Ege.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to UYEN SMET whose telephone number is (571) 272-2267. The examiner can normally be reached M-F, 9 AM-5 PM.
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/UYEN SMET/
[AltContent: connector] Primary Examiner, Art Unit 2824
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