DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-8, 13-15, and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mohammad (U.S. Patent No. 5,426,316).
Regarding to claim 1, Mohammad teaches a method for manufacturing a semiconductor device, comprising:
providing a substrate (Fig. 2G, element 100);
forming at least one silicon layer on top of the substrate (Fig. 2G, one of silicon layers in the Si/SiGe superlattice 104);
forming at least one silicon-germanium layer on top of the at least one silicon layer (Fig. 2G, element 106), the at least one silicon-germanium layer including at least one n-type dopant (column 3, lines 55-59, a p-type layer is illustrated in the figure, however, lay 106 could be n-type when the device is PNP); and
forming the semiconductor device having the at least one silicon layer and the at least one silicon-germanium layer (Fig. 2G, a Triple Heterojunction Bipolar Transistor is formed).
Regarding to claim 2, Mohammad teaches stacking a plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer, the semiconductor device including the stacked plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer (Fig. 2G, Si/SiGe superlattice 104, Si and SiGe layers alternatively stacked).
Regarding to claim 4, Mohammad teaches forming at least one p-type doped region within the at least one silicon layer, the at least one p-type doped region being disposed adjacent the at least one silicon-germanium layer (column 2, lines 55-57, Si/SiGe superlattice stacks are doped, in case the device is PNP HBT, the dopant is p-type).
Regarding to claim 5, Mohammad teaches stacking a plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer (Fig. 2G, Si/SiGe superlattice 104, Si and SiGe layers alternatively stacked), the at least one silicon layer having the at least one p-type doped region formed within the at least one silicon layer (column 2, lines 55-57, Si/SiGe superlattice stacks are doped, in case the device is PNP HBT, the dopant is p-type); the semiconductor device including the stacked plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer (Fig. 2G, in case the device is PNP HBT, Si layer 120 is p-type, superlattice 104 is p-type, SiGe layer 106 is n-type, superlattice 108 is p-type, and Si layer 110 is p-type).
Regarding to claim 6, Mohammad teaches one or more silicon-germanium layers in the stacked plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer is configured to be adjacent to one or more p-type doped regions formed within silicon layers adjacent to the one or more silicon-germanium layers (column 2, lines 55-57, Si/SiGe superlattice stacks are doped, in case the device is PNP HBT, the dopant is p-type).
Regarding to claim 7, Mohammad teaches the one or more p-type doped regions include one or more p-type dopants, the one or more p-type dopants include at least one of the following: boron, carbon, boron and carbon, and any combination thereof (column 3, lines 39-41, moreover, boron is commonly used as p-type dopant and phosphorus is commonly used as n-type dopant).
Regarding to claim 8, Mohammad teaches forming at least one tensile layer on a bottom of the at least one silicon layer (germanium has greater lattice constant (5.658 Å) than silicon (5.43 Å), thus silicon layers are tensile strained).
Regarding to claim 13, Mohammad teaches the n-type dopant includes at least one of the following: phosphorous, arsenic, antimony, bismuth, lithium, and any combination thereof (column 3, line 9, moreover, phosphorus or Arsenic is commonly used as n-type dopant).
Regarding to claim 14, Mohammad teaches a semiconductor device, comprising:
a substrate (Fig. 2G, element 100);
at least one silicon layer on top of the substrate (Fig. 2G, one of silicon layers in the Si/SiGe superlattice 104);
least one silicon-germanium layer on top of the at least one silicon layer (Fig. 2G, element 106), the at least one silicon-germanium layer including at least one n-type dopant (column 3, lines 55-59, a p-type layer is illustrated in the figure, however, lay 106 could be n-type when the device is PNP); and
Regarding to claim 15, Mohammad teaches a stacked plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer (Fig. 2G, Si/SiGe superlattice 104, Si and SiGe layers alternatively stacked. Further, the stack is formed on silicon layer 102).
Regarding to claim 17, Mohammad teaches forming at least one p-type doped region within the at least one silicon layer, the at least one p-type doped region being disposed adjacent the at least one silicon-germanium layer (column 2, lines 55-57, Si/SiGe superlattice stacks are doped, in case the device is PNP HBT, the dopant is p-type).
Regarding to claim 18, Mohammad teaches stacking a plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer (Fig. 2G, Si/SiGe superlattice 104, Si and SiGe layers alternatively stacked), the at least one silicon layer having the at least one p-type doped region formed within the at least one silicon layer (column 2, lines 55-57, Si/SiGe superlattice stacks are doped, in case the device is PNP HBT, the dopant is p-type); one or more silicon-germanium layers in the stacked plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer is configured to be adjacent to one or more p-type doped regions formed within silicon layers adjacent to the one or more silicon-germanium layers (Fig. 2G, in case the device is PNP HBT, Si layer 120 is p-type, superlattice 104 is p-type, SiGe layer 106 is n-type, superlattice 108 is p-type, and Si layer 110 is p-type).
Regarding to claim 19, Mohammad teaches the one or more p-type doped regions include one or more p-type dopants, the one or more p-type dopants include at least one of the following: boron, carbon, boron and carbon, and any combination thereof (column 3, lines 39-41, moreover, boron is commonly used as p-type dopant and phosphorus is commonly used as n-type dopant).
Claims 1-2, 8, and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bu et al. (U.S. Patent No. 10,224,429).
Regarding to claim 1, Bu teaches a method for manufacturing a semiconductor device, comprising:
providing a substrate (Fig. 7, element 5);
forming at least one silicon layer on top of the substrate (Fig. 7, element 8b; column 5, line 27);
forming at least one silicon-germanium layer on top of the at least one silicon layer, the at least one silicon-germanium layer including at least one n-type dopant (Fig. 7, element 9b; column 5, lines 29-30); and
forming the semiconductor device having the at least one silicon layer and the at least one silicon-germanium layer (Fig. 7, column 5, lines 10-12).
Regarding to claim 2, Bu teaches stacking a plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer (Fig. 7, column 11, lines 63-65, silicon-germanium layers 7b, 9b, and 11b formed on top of the at least one silicon layer), the semiconductor device including the stacked plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer (Fig. 7).
Regarding to claim 8, Bu teaches forming at least one tensile layer on a bottom of the at least one silicon layer (germanium has greater lattice constant (5.658 Å) than silicon (5.43 Å), thus silicon layers are tensile strained).
Regarding to claim 13, Bu teaches the n-type dopant includes at least one of the following: phosphorous, arsenic, antimony, bismuth, lithium, and any combination thereof (column 8, lines 60-63).
Regarding to claim 14, Bu teaches a semiconductor device, comprising:
a substrate (Fig. 7, element 5);
at least one silicon layer on top of the substrate (Fig. 7, element 8b; column 5, line 27);
least one silicon-germanium layer on top of the at least one silicon layer, the at least one silicon-germanium layer including at least one n-type dopant (Fig. 7, element 9b; column 5, lines 29-30); and
Regarding to claim 15, Bu teaches a stacked plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer (Fig. 7, column 11, lines 63-65, silicon-germanium layers 7b, 9b, and 11b formed on top of the at least one silicon layer).
Claims 1-2, 4-8, 13-15, and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chu et al. (U.S. Patent No. 5,906,951).
Regarding to claim 1, Chu teaches a method for manufacturing a semiconductor device, comprising:
providing a substrate (Fig. 5, element 12);
forming at least one silicon layer on top of the substrate (Fig. 5, element 16);
forming at least one silicon-germanium layer on top of the at least one silicon layer (Fig. 5, element 18), the at least one silicon-germanium layer including at least one n-type dopant (Fig. 5, column 3, lines 51-52, doped region 42 of layer 18); and
forming the semiconductor device having the at least one silicon layer and the at least one silicon-germanium layer (Fig. 5, a FET device).
Regarding to claim 2, Chu teaches stacking a plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer, the semiconductor device including the stacked plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer (Fig. 5, stack 17/18).
Regarding to claim 4, Chu teaches forming at least one p-type doped region within the at least one silicon layer, the at least one p-type doped region being disposed adjacent the at least one silicon-germanium layer (Fig. 5).
Regarding to claim 5, Chu teaches stacking a plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer, the at least one silicon layer having the at least one p-type doped region formed within the at least one silicon layer (Fig. 5, stack of SiGe layer 14, Si layer 15, doped SiGe layer 18, Si layer 19); the semiconductor device including the stacked plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer (Fig. 5).
Regarding to claim 6, Chu teaches one or more silicon-germanium layers in the stacked plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer is configured to be adjacent to one or more p-type doped regions formed within silicon layers adjacent to the one or more silicon-germanium layers (Fig. 5, p-type doped region 48).
Regarding to claim 7, Chu teaches the one or more p-type doped regions include one or more p-type dopants, the one or more p-type dopants include at least one of the following: boron, carbon, boron and carbon, and any combination thereof (Fig. 5, boron B+).
Regarding to claim 8, Chu teaches forming at least one tensile layer on a bottom of the at least one silicon layer (germanium has greater lattice constant (5.658 Å) than silicon (5.43 Å), thus silicon layers are tensile strained).
Regarding to claim 13, Chu teaches the n-type dopant includes at least one of the following: phosphorous, arsenic, antimony, bismuth, lithium, and any combination thereof (Fig. 5, phosphorus P+ or Arsenic As+).
Regarding to claim 14, Chu teaches a semiconductor device, comprising:
a substrate (Fig. 5, element 12);
at least one silicon layer on top of the substrate (Fig. 5, element 16);
least one silicon-germanium layer on top of the at least one silicon layer (Fig. 5, element 18), the at least one silicon-germanium layer including at least one n-type dopant (Fig. 5, column 3, lines 51-52, doped region 42 of layer 18); and
Regarding to claim 15, Chu teaches a stacked plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer (Fig. 5, stack 17/18).
Regarding to claim 17, Chu teaches forming at least one p-type doped region within the at least one silicon layer, the at least one p-type doped region being disposed adjacent the at least one silicon-germanium layer (Fig. 5, p-type doped region 48).
Regarding to claim 18, Chu teaches stacking a plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer, the at least one silicon layer having the at least one p-type doped region formed within the at least one silicon layer; one or more silicon-germanium layers in the stacked plurality of the at least one silicon-germanium layer formed on top of the at least one silicon layer is configured to be adjacent to one or more p-type doped regions formed within silicon layers adjacent to the one or more silicon-germanium layers (Fig. 5, p-type doped region 48).
Regarding to claim 19, Chu teaches the one or more p-type doped regions include one or more p-type dopants, the one or more p-type dopants include at least one of the following: boron, carbon, boron and carbon, and any combination thereof (Fig. 5, boron B+).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. (U.S. Patent No. 5,906,951), as applied to claim 1 above.
Regarding to claim 3, Chu is silent as to a difference in thickness between the silicon layer and the silicon-germanium layer. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a thickness of at least one silicon layer to be greater than a thickness of at least one silicon-germanium layer for satisfying a functionality desire, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. (U.S. Patent No. 5,906,951), as applied to claim 14 above.
Regarding to claim 16, Chu is silent as to a difference in thickness between the silicon layer and the silicon-germanium layer. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a thickness of at least one silicon layer to be greater than a thickness of at least one silicon-germanium layer for satisfying a functionality desire, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Allowable Subject Matter
Claims 9-12 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 9, the prior art fails to anticipate or render obvious the claimed limitations including “the forming the at least one tensile layer includes forming at least one n-type doped silicon layer on top of the substrate; forming at least one p-type stop layer on top of the n-type doped silicon layer; and removing at least a portion of then-type doped silicon layer” in combination with the limitation recited in claims 1, 4, and 8.
Regarding to claim 20, the prior art fails to anticipate or render obvious the claimed limitations including “at least one tensile layer formed on a bottom of the at least one silicon layer; wherein the at least one tensile layer is formed by forming at least one n-type doped silicon layer on top of the substrate; forming at least one p-type stop layer on top of the n-type doped silicon layer; and removing at least a portion of then-type doped silicon layer” in combination with the limitation recited in claims 14 and 17.
Pertinent Art
For the benefits of the Applicant, US-7906408-B2, US-20210091245-A1, US-6982208-B2, US-4771326-A, US-5357119-A, US-6207978-B1, US-9922941-B1, US-9502420-B1, US-8822282-B2, US-10361243-B2 US-20140077339-A1, US-11362217-B1, and US-11205698-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose at least one silicon-germanium layer including at least one n-type dopant.
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897
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