DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgement of preliminary amendment dated 02 October 2024 with independent claims 1, 10 and 18 of which claims 2-3 are currently canceled while currently adding new claims 4-22.
Pending claims 1 and 4-22 are examined on their merits infra.
35 U.S.C. 120 Benefit Claim Denied, Filing Date 06/17/24 Accorded
Instant application 18/745,760 was filed 06/17/24, claiming benefit to application 17/234,238 in the Application Data Sheet as required by 37 C.F.R. 1.78. Although applicant, in the first paragraph of their Specification filed 06/17/24, listed application 17/234,138 as their most recent benefit application in the chain of continuity, the listing in the Specification is ineffective. The Office mailed a Filing Receipt on 07/02/24 listing application 17/234,238 as the most recent application in the chain of continuity. MPEP 211.02(I).
In application 17/234,238, a nonfinal rejection mailed 06/08/23 setting a 3-month shortened statutory time period for reply. A timely response was due 09/08/23. Applicant did not reply and did not petition for any extensions of time. The application was abandoned 09/09/23.
Because instant application was filed on or after the date of abandonment of 17/234,238, instant application does not qualify to claim benefit to application 17/234,238 due to lack of copendency. MPEP 211.01(b)(I). Additionally, the attempted benefit claim to 17/234,238 also fails to comply with basic requirements of 35 U.S.C. 120, namely, "which names an inventor or joint inventor in the previously filed application." The inventors are not the same, the applicant is not the same, the disclosures are not the same. MPEP 211.01(II)
Furthermore, the next most recent benefit claim is to application 16/877,345 (to which 17/234,238 was allegedly its continuation). Application 16/877,345 was patented on April 20, 2021, which was also not copending with instant application.
It is noted applicant on July 10, 2025, about one year after the Office's mailing of the filing receipt on 07/02/24, attempted the mere filing of a corrected Application Data Sheet to strikethrough application 17/234,238 and replace with 17/234,138; however, such amendment to the ADS is ineffective.
Therefore, instant application is only entitled to its actual filing date: 06/17/24.
Two Information Disclosure Statements
The two information disclosure statements submitted on 17 June 2024 were filed before first Office action. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4–9, 10–17, and 12–13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and claims 4-9 depending therefrom.
Claim 1 recites “a distance between the oxide layer on the top surfaces of adjacent fin structures” that is greater than “a distance between the oxide layer on inner sidewall surfaces of adjacent fin structures.”
The specification never identifies those two distances, never states which edges are the measuring points, and never uses the word “distance” for an inter-fin comparison of oxide portions.
FIG. 12A instead labels widths on one fin:
114Aw1 = width of each top portion 114A3;
114Aw2 = sum of the widths of one fin structure 106A and its sidewalls;
114Aw1 > 114Aw2, and 114A3 extends laterally beyond sidewalls of 114A4 by about 0.1 nm to about 1 nm.
Those are occupied widths of a single fin, not gaps between adjacent fins. If 114Aw1 and 114Aw2 are treated as the claim “distances,” the claim language (“between … adjacent”) does not match the specification. If the claim instead means the open gaps (pitch minus those widths), FIG. 12A yields the opposite inequality (gap at the tops smaller than gap at the inner sidewalls) because 114Aw1 > 114Aw2.
FIG. 2A can be read as Dtop ≈ Dside (conformal inner walls) while FIG. 12A shows Dtop < Dside.
PNG
media_image1.png
746
637
media_image1.png
Greyscale
PNG
media_image2.png
800
464
media_image2.png
Greyscale
A person of ordinary skill cannot determine the metes and bounds with reasonable certainty. Nautilus, Inc. v. Biosig Instruments, Inc., 572 U.S. 898 (2014).
For purpose of examination on the merits Dtop and Dside are the distances considered in claim 1.
Claims 4–9 inherit the indefiniteness.
Claims 10 and claims 11-17 depending therefrom.
Claim 10 recites “a first distance of the upper sidewall from a top surface of the fin structure” that is less than “a second distance of the upper sidewall from a top surface of the isolation region.”
“Upper sidewall” is not defined. If it means the entire sidewall above STI, the second distance is zero and the inequality cannot be met. If it means only a short upper band, the claim does not say where that band ends. The specification describes thicker oxide on the fin top and thinner oxide on sidewalls of the portion extending above STI; it does not describe or number d1 and d2. Scope is not reasonably certain and the distances starting point appear rather arbitrary.
Claim 10 also recites “substrate” without the article “a.”
Claims 11-17 inherit this indefiniteness.
Claims 12-13 lack antecedent basis.
Claim 12 recites “a gate electrode on the dielectric layer” and depends from claim 10. Claim 10 does not recite a dielectric layer. The dielectric layer is introduced in claim 11.
Claim 13 depends from claim 12 and likewise lacks antecedent basis for “the dielectric layer.”
For examination on the merits only, claims 12 and 13 are treated as depending from claim 11. Applicant must amend the dependency.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 4–9, and 10–17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1
The specification describes (i) a first thickness on fin tops greater than a second thickness on sidewalls (114At1/114At3 > 114At2/114At4) and (ii) in FIG. 12A, a width 114Aw1 of each top portion 114A3 greater than a width 114Aw2 of one fin plus its sidewalls. It does not describe “a distance between the oxide layer on the top surfaces of adjacent fin structures” that is greater than “a distance between the oxide layer on inner sidewall surfaces of adjacent fin structures.”
Possession of the claimed inter-fin distance comparison is not shown. Ariad Pharm., Inc. v. Eli Lilly & Co., 598 F.3d 1336 (Fed. Cir. 2010) (en banc). Using 114Aw1/114Aw2 as those “distances” is a mapping the specification does not make; those labels are single-fin widths. Claims 4–9 inherit the defect.
Claim 10
The specification does not describe a first vertical distance of an “upper sidewall” from the fin top that is less than a second vertical distance of that upper sidewall from the STI top. Thickness and “portions extending above STI” are described. The two-distance comparison is not. Claims 11–17 inherit the defect as to that limitation.
Enablement is not separately rejected. A POSITA can grow thicker top oxide on fins. The defect is possession of the recited geometric comparisons.
Prior art rejections based on Primary reference of Chang.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4-22 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by US 2021/0257259 A1 to Chang et al. (“Chang”).
Item-by-item matching is bypassed because applicant is familiar with this prior-art due to an attempt to claim domestic benefit as explained supra.
Prior art rejections based on Primary reference of Colinge.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 18-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2014/0353731 A1 to Colinge et al. (“Colinge”).
PNG
media_image3.png
572
1019
media_image3.png
Greyscale
Regarding independent claim 18, Colinge teaches of a semiconductor device (see title), comprising:
a fin structure 20+40+24 (“substrate” + “SiGeO” + “silicon layer”; Figure 2C; paragraph 0035; the part of 20 that creates the raised-up portion and SiGeO and the silicon layer form a fin structure); and
an oxide layer 42 (“gate dielectric”; Figure 2C; paragraph 0036 states that this the gate dielectric similar in material to Figure 1I that as taught in paragraph 0029 may be an oxide layer in at least one embodiment) on an upper portion (see Figure 2C) of the fin structure 20+40+24, comprising:
a first portion on a top surface of the fin structure 20+40+24 and comprising a first thickness (see Examiner’s Annotated Figure 2C supra: Dtop is thicker than Dside); and
a second portion on sidewalls of the fin structure 20+40+24 and comprising a second thickness (see Examiner’s Annotated Figure 2C supra: Dtop is thicker than Dside) less than the first thickness (as illustrated), wherein the first portion Dtop of the oxide layer extends laterally beyond (see Examiner’s Annotated Figure 2C supra) sidewalls of the second portion Dside.
Regarding claim 19, Colinge teaches wherein the second portion Dside of the oxide layer has a conformal second thickness (on the part that defines Dside the required thickness is less than Dtop and for the distance of Dside that has that less thickness does appear conformal).
Regarding claim 20, Colinge teaches wherein a lower portion (i.e., closer to substrate 2o) of the fin structure 20+40+24 is surrounded by an isolation region 28 (“isolation region”; Figure 2C; paragraph 0028).
Regarding claim 21, Colinge teaches wherein a third portion of the oxide layer 42 is disposed on a top surface (see Figure 2C) of the isolation region 28.
Regarding claim 22, Colinge teaches further comprising an amorphous silicon layer on the top surface of the fin structure.
Prior art rejections based on Primary reference of Chung.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2016/0104705 A1 to Chung et al. (“Chung”).
PNG
media_image4.png
339
654
media_image4.png
Greyscale
Regarding independent claim 1, Chung teaches of a semiconductor structure (see title), comprising:
a substrate 110 (“substrate”; Figure 4; paragraph 0052);
adjacent fin structures 130-1 / 130-2 (“first fin” / “second fin”; Figure 4; paragraph 0089; this paragraph explains that the fin structure may both be tapered shape) disposed on the substrate 110; and
an oxide layer 174 (“dielectric”; Figure 4; may be oxide as stated in paragraph 0067), comprising:
a first thickness (see 174-2b in Figure 4) on top surfaces of the adjacent fin structures 130-1 / 130-2 (i.e., selecting the embodiment where both fins are tapered); and
a second thickness (see 174-1) on inner and outer sidewall surfaces of the adjacent fin structures 130-1 / 130-2 (i.e., selecting the embodiment where both fins are tapered), wherein the second thickness 174-1 is less than the first thickness 172-2b, and wherein a distance between the oxide layer on the top surfaces 174-2b of adjacent fin structures 103-1 / 130-2 is greater (see Examiner’s Annotated Figure 4 of Chung supra: see longer dotted line) than a distance (see smaller dotted line) between the oxide layer on inner sidewall 174-1 surfaces of adjacent fin structures 130-1 / 130-2.
Regarding claim 4, Chung teaches further comprising an isolation region 120 (“isolation film” Figure 4; paragraph 0059) disposed between the adjacent fin structures 103-1/130-2.
Regarding claim 5, Chung teaches wherein the oxide layer 174 is disposed on a top surface (see Figure 4) of the isolation region 120.
Regarding claim 6, Chung teaches of a doped silicon layer (see paragraph 0014: there are source/drain epi structures) on top surfaces of the adjacent fin structures 130-1 / 130-2.
Regarding claim 7, Chung teaches wherein the doped silicon layer (i.e., epi source/drain regions) is in contact with a bottom surface (i.e., given the broadest reasonable interpretation: no orientation is defined and no coordinate system is defined or set-up in the claim language. As such, when the epi-source/drain regions are formed in some orientation or coordinate system they may be indirectly contacting the oxide layer 174) of the oxide layer 174.
Regarding claim 8, Chung teaches in Figure 4 further comprising; a dielectric layer 28 on (i.e., “on” is broad and therefore 28 appears to be on 174) the oxide layer 174; and a gate electrode 172 on the dielectric layer 28.
Regarding claim 9, Chung teaches further comprising spacers (see paragraph 0014 and other drawings like Figures 23-24; there may be spacers) on sidewalls of the gate electrode 172, wherein the oxide layer 174 extends under (i.e., given the broadest reasonable interpretation: no orientation is defined and no coordinate system is defined or set-up in the claim language. As such, 174 may be in some orientation or coordinate system under the spacers) the spacers (see paragraph 0014 and other drawings like Figures 23-24; there may be spacers).
Regarding independent claim 10, Chung teaches in Figure 4 of a semiconductor structure (see title), comprising:
a substrate 110;
a fin structure 130-1 / 130-2 (see paragraph 0089 these fins may both be tapered) disposed on the substrate 110;
an isolation region 120 surrounding the fin structure 130-1 / 130-2; and
an oxide layer 174, comprising:
a first portion 174-2b with a first thickness (see Figure 4) disposed on a top surface of the fin structure 130-1 / 130-2; and
a second portion 174-1 with a second thickness (see Figure 4) disposed on an upper sidewall (give that 130-1 and 130-2 are both tapered) of the fin structure 130-1 / 130-2, wherein the first thickness 174-2b is greater than (see Figure 4) the second thickness 174-1, and wherein a first distance of the upper sidewall from a top surface of the fin structure is less than a second distance of the upper sidewall from a top surface of the isolation region (i.e., as explained supra – these distance appear arbitrary with respect to starting points: as such there exists a point where said inequality is true).
Regarding claim 11, Chung teaches further comprising a dielectric layer 178 on the first and second portions of the oxide layer 174.
Regarding claim 12, Chung teaches further comprising a gate electrode 172 on the dielectric layer 178.
Regarding claim 13, Chung teaches further comprising spacers 178 on sidewalls of the gate electrode 172, wherein the oxide layer 174 extends under (i.e., given the broadest reasonable interpretation: no orientation is defined and no coordinate system is defined or set-up in the claim language. As such, 174 may be in some orientation or coordinate system under the spacers) the spacers 178.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ELISEO RAMOS-FELICIANO can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
09 September 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
Prosecution Insights