Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18,745,977 filed on June 17, 2024.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claim 1 is rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 1 of prior U.S. Patent No. 12,016,211. This is a statutory double patenting rejection.
Claims of Instant Application
Claims of U.S. Patent 12,016,211
Explanation of Differences
1
1
‘211 Claim 1 encompasses the claimed subject matter
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim (US Pub # 2005/0158925), Akimoto et al. (US Pub # 2010/0090217), Kwak et al. (US Pub # 2006/0043365), Kim et al. (US Pub # 2004/0056251), Kang et al. (US Pub # 2021/0320268), Sim et al. (U.S. Pub # 2017/0141169), Tanaka (U.S. Pub# 2014/0326994), Akimoto (U.S. Pat # 8,158,975) and Nagata (U.S. Pub # 2007/0235777).
Kim discloses a display device (Fig. 1) comprising thin film transistor (TFT) array panel, wherein the thin film transistor (TFT) array panel comprising a substrate (110), a gate line (121) formed on the substrate and including a gate electrode (124), a first insulating layer (140) formed on the gate line (121), a semiconductor layer (151) formed on the first insulating layer (140), ohmic contacts (161, 165) formed on the semiconductor layer (151), source (173) and drain electrodes (175) formed on the ohmic contacts (161, 165) and disposed opposite each other with respect to the semiconductor layer (151), a second insulating layer (221) formed on the source and the drain electrodes (173, 175) and having a first contact hole (182 and 185) exposing a portion of the drain electrode (175) and an opening exposing the first portion of the semiconductor layer (151) and having an edge coinciding with edges of the source and the drain electrodes (175), a pixel electrode (190) formed on the second insulating layer (221).
Akimoto discloses a semiconductor device (Fig. 1A) comprising: a gate insulating layer (102), a gate electrode layer (111) provided on one side of the gate insulating layer (102), an oxide semiconductor layer (113) provided on the other side of the gate insulating layer (102), and a source electrode layer (117a) and a drain electrode layer (117b), each comprising a first conductive layer (114a) including aluminum (0049) in contact with the gate insulating layer (102), a second conductive layer (114b) including a high-melting-point metal material over the first conductive layer (114a), and a barrier layer (1 16a), the barrier layer including aluminum oxide at an edge portion of the first conductive layer, wherein the oxide semiconductor layer (113) is in contact with the second conductive layer (114b) and the barrier layer (116a).
Kwak discloses a display device comprising thin film transistor array panel, wherein the thin film transistor array panel comprising, a gate line (121), a first insulator (110) disposed on the gate line (121), a semiconductor (151) disposed on the first insulator (110), an ohmic contact (161) disposed on the semiconductor (151), a first conductor layer ((0023) disposed on the ohmic contact (161), a second conductor layer including a first portion disposed on the first conductor layer and a second portion contacting the ohmic contact, a second insulator (0023) disposed on the second conductor layer and having a contact hole exposing the second conductor layer at least in part and a pixel electrode (190) disposed on the second insulator and contacting the second conductor layer through the contact hole.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHSEN AHMADI whose telephone number is (571)272-5062. The examiner can normally be reached M-F: 9:00am-5:00pm.
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/MOHSEN AHMADI/ Primary Examiner, Art Unit 2896
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