DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Tung (US 6391698).
With regard to claim 1, Tung teaches, in Figures 1A-1G, a manufacturing method of a semiconductor device, comprising: forming a trench (17) in a semiconductor substrate (11); and forming a gate structure (16, 18) on the semiconductor substrate, wherein the gate structure comprises: a gate electrode (18), wherein a first portion of the gate electrode is disposed in the trench (portion of 18 below the top surface of 16 in the figures), and a second portion of the gate electrode (portion of 18 overlying 16 in the figures) is disposed outside the trench; a first gate oxide layer (18A; column 3, lines 15-20) disposed between the gate electrode and the semiconductor substrate, wherein at least a portion of the first gate oxide layer is disposed in the trench (see figures); and a second gate oxide layer (16) disposed between the second portion of the gate electrode and the semiconductor substrate in a vertical direction (see figures), wherein a thickness of the second gate oxide layer (column 2, lines 60-65) is greater than a thickness of the first gate oxide layer (column 3, lines 15-20).
With regard to claim 2, Tung teaches, in Figures 1A-1G, that a method of forming the gate structure comprises: forming a pad oxide layer (14, 16) on the semiconductor substrate; and performing an etching process to the pad oxide layer and the semiconductor substrate for forming the trench (column 2, line 65 - column 3, line 10), wherein the pad oxide layer is etched to be a patterned oxide layer by the etching process (see Figure 1E).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 4, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tung (US 6391698) in view of Kawaguchi (US 2012/0319196).
With regard to claim 3, Tung teaches most of the limitations of this claim, as set forth above with regard to claim 2.
Tung also teaches, in Figures 1A-1G, that the method of forming the gate structure further comprises: forming a gate material layer (18) on the semiconductor substrate after the etching process, wherein the gate material layer is partly formed in the trench and partly formed outside the trench, and the patterned oxide layer (16) is located between the gate material layer and the semiconductor substrate in the vertical direction.
Tung does not explicitly teach performing a patterning process to the gate material layer and the patterned oxide layer, wherein the gate material layer is patterned to be the gate electrode by the patterning process, and the patterned oxide layer is patterned to be the second gate oxide layer by the patterning process.
Kawaguchi teaches, in Figures 6A-7A, performing a patterning process to the gate material layer (122) and the patterned oxide layer (120 formed outside the trench), wherein the gate material layer is patterned to be the gate electrode by the patterning process, and the patterned oxide layer is patterned to be the second gate oxide layer by the patterning process ([0050]), “to increase the dopant concentration only in desired regions without increasing the second conductivity type dopant concentration in the channel region 108 to a level higher than necessary, it is possible to prevent actions like those of parasitic transistors, and it is possible to prevent phenomena such as hump and kink. This enables the subthreshold characteristics of transistor to be improved,” ([0053]).
Therefore, it would have been obvious to the ordinary artisan at the effective date of filing to combine the method of Tung with the gate patterning process of Kawaguchi to prevent phenomena such as hump and kink, thus enabling the subthreshold characteristics of transistor to be improved.
With regard to claim 4, Tung teaches, in Figures 1A-1G, that the method of forming the gate structure further comprises: forming the first gate oxide layer after the etching process and before the step of forming the gate material layer (column 3, lines 10-20).
With regard to claim 10, Tung teaches most of the limitations of this claim, as set forth above with regard to claim 1.
Tung does not explicitly teach forming a spacer structure on a sidewall of the gate structure, wherein the space structure is located on a sidewall of the second portion of the gate electrode and a sidewall of the second gate oxide layer.
Kawaguchi teaches, in Figures 7A-7B, forming a spacer structure (24) on a sidewall of the gate structure (122), wherein the space structure is located on a sidewall of the second portion of the gate electrode (portion above surface of 102 in the figures) and a sidewall of the second gate oxide layer (120 above surface of 102 in the figures), “to increase the dopant concentration only in desired regions without increasing the second conductivity type dopant concentration in the channel region 108 to a level higher than necessary, it is possible to prevent actions like those of parasitic transistors, and it is possible to prevent phenomena such as hump and kink. This enables the subthreshold characteristics of transistor to be improved,” ([0053]).
Therefore, it would have been obvious to the ordinary artisan at the effective date of filing to combine the method of Tung with the sidewall spacer of Kawaguchi to prevent phenomena such as hump and kink, thus enabling the subthreshold characteristics of transistor to be improved.
Claim(s) 5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tung (US 6391698).
With regard to claim 5, Tung teaches most of the limitations of this claim, as set forth above with regard to claim 2.
Tung also teaches, in Figures 1A-1G, forming two drift regions (13A, 13B; each located at either side of the trench) in the semiconductor substrate, wherein a part of each of the two drift regions is removed by the etching process for forming the trench (see Figs 1D-1E), and the two drift regions are located at two opposite sides of the trench in a horizontal direction, respectively (see figures).
Tung does not explicitly teach that the drift regions are formed after the step of forming the pad oxide layer and before the etching process.
It has been held that the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. See Ex parte Rubin, 128 USPQ 440 (Bd. App. 1959). See also In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946) (selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930) (Selection of any order of mixing ingredients is prima facie obvious.). Since there is no evidence in the record of any new or unexpected results stemming from the claimed order of performing process steps, the selection of the claimed order of steps is found to be obvious.
With regard to claim 6, Tung teaches, in Figures 1A-1G, that a bottom of each of the two drift regions is lower than a bottom of the trench in the vertical direction (see figures).
With regard to claim 7, Tung teaches, in Figures 1A-1G, that the first portion of the gate electrode is located between the two drift regions in the horizontal direction, and a portion of the first gate oxide layer is located between the first portion of the gate electrode and each of the two drift regions in the horizontal direction (see figures).
With regard to claim 8, Tung teaches, in Figures 1A-1G, that the second gate oxide layer is located between the second portion of the gate electrode and each of the two drift regions in the vertical direction (see figures).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tung (US 6391698) in view of Yamashita et al. (US 2017/0373183).
With regard to claim 9, Tung teaches most of the limitations of this claim, as set forth above with regard to claim 1.
Tung does not explicitly teach that a first portion of the first gate oxide layer is located in the trench, and a second portion of the first gate oxide layer is located between the second portion of the gate electrode and the second gate oxide layer in the vertical direction.
Yamashita teaches, in Figures 12 and 13, that a first portion (portion of IF3 in the trench) of the first gate oxide layer (IF3) is located in the trench, and a second portion (portion of IF3 overlying IF2 and SR) of the first gate oxide layer is located between the second portion (portion of PF2 overlying GOX1 and SR) of the gate electrode (PF2) and the second gate oxide layer (IF2) in the vertical direction, “to prevent the gate insulating film GOX1 from being broken on the corner parts of the trench TR where the electric field concentration is liable to occur. Thereby, it is possible to improve the reliability of the semiconductor device,” ([0048]).
Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the method of Tung with the oxide layer formation of Yamashita to improve the reliability of the semiconductor device.
Conclusion
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/RAJ R GUPTA/Primary Examiner, Art Unit 2893
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