Prosecution Insights
Last updated: October 02, 2026
Application No. 18/746,087

MAGNETORESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAME

Non-Final OA §102
Filed
Jun 18, 2024
Priority
Apr 29, 2024 — TW 113115881
Examiner
PHAM, LONG
Art Unit
Tech Center
Assignee
United Microelectronics Corp.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1530 granted / 1671 resolved
+31.6% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
40 currently pending
Career history
1697
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
42.7%
+2.7% vs TC avg
§102
39.7%
-0.3% vs TC avg
§112
10.3%
-29.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1671 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 7-12 in the reply filed on 7/6/26 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 7, 8, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hashemi et al. (US pub 20240112712). With respect to claim 7, Hashemi et al. teach a magnetoresistive random access memory (MRAM) device, comprising (see figs. 1-1, particularly figs. 2, 10, and 11 and associated text): a spin orbit torque (SOT) layer 210 on a substrate 101; a magnetic tunneling junction (MTJ) 212,214,216 on the SOT layer; a first cap layer (lateral part of 218) adjacent to the MTJ; and a second cap layer (vertical part of 218) adjacent to the first cap layer, wherein a thickness of the first cap layer is greater than a thickness of the second cap layer. With respect to claim 8, Hashemi et al. teach a top electrode (TE) 204 on the MTJ; and an inter-metal dielectric (IMD) layer around the second cap layer (see para 0031). With respect to claim 10, Hashemi et al. teach a width of the MTJ is less than a width of the SOT layer. See fig. 2 and associated text. Claim(s) 7 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuo et al. (US pub 20240016067). With respect to claim 7, Kuo et al. teach a magnetoresistive random access memory (MRAM) device, comprising (see figs. 1-4, particularly fig. 2 and associated text): a spin orbit torque (SOT) layer 108 on a substrate 100; a magnetic tunneling junction (MTJ) 116 on the SOT layer; a first cap layer 120a adjacent to the MTJ; and a second cap layer 118a adjacent to the first cap layer, wherein a thickness of the first cap layer is greater than a thickness of the second cap layer. With respect to claim 7, Kuo et al. teach a bottom surface of the second cap layer is lower than a bottom surface of the first cap layer. See fig. 2 and associated text. Allowable Subject Matter Claims 9 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Examiner’s Cited References The cited references generally show the similar or related structure having a stacked of a MTJ layer, a SOI layer, a substrate, having first and second cap layers adjacent to the MTJ layer having different thicknesses as presently claimed by applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jun 18, 2024
Application Filed
Sep 14, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.5%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1671 resolved cases by this examiner. Grant probability derived from career allowance rate.

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