The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of the embodiment of figures 1-2 in the reply filed on 03/01/2022 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of “second transistor”, as recited in claims 1 and 13, is unclear as to which transistor applicants refer because the detailed description does correlate the second transistor to any structure depicted in the drawings.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 9-20, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Noguchi (6,649,980) and Rao (2008/0179664). Regarding claims 1, 13 and 18, Noguchi teaches in figure 1 and related text a semiconductor structure, comprising:
a first transistor (located below gate 20) comprising:
a gate 20 extending in a first direction;
a first active region (the middle of element 16) arranged in a first layer and extending in a second direction perpendicular to the first direction; and
a first conductive line (the right side of element 16) and a second conductive line (the left side of element 16) arranged in the first layer on two sides of the first active region; and
a second transistor (located below gate 20) arranged over the first transistor and comprising:
the gate 20;
a second active region 24 arranged in a second layer over the first layer and extending in the second direction; and
a third conductive line (the right side of element 24) and a fourth conductive line (the left side of element 24) arranged in the second layer on two sides of the second active region,
wherein, from a top-view perspective, the gate 20 has a first portion, extending beyond the first active region (the middle of element 16) in the first direction by a first length, and a second portion extending beyond the first active region in a third direction, opposite to the first direction, by a second length greater than the first length (selected as such),
wherein, from a top-view perspective, at least one of the first, second, third and fourth conductive lines has a third portion extending beyond the first active region (the middle of element 16) in the third direction by a third length, and a fourth portion extending beyond the first active region in the first direction by a fourth length greater than the third length (selected as such).
Noguchi does not explicitly state that the second length is greater than the first length and that the fourth length is greater than the third length.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the second length greater than the first length the fourth length greater than the third length, in Noguchi’s device, in order to form the device as intended by Noguchi.
Regarding claims 13 and 18, Noguchi teaches in figures 1, 2 and related text using a first power rail 13 and a second power rail (26 or 27, see also element 36 in figure 2),a and wherein the first power rail and the second power rail are configured to supply a first voltage Vss and a second voltage Vdd, respectively.
Regarding claim 4, Noguchi teaches in figure 1 and related text that the first and second power rails overlap the first and second active regions.
Regarding claim 9, Noguchi teaches in figure 2 and related text a second conductive via electrically connecting the second conductive line to the third conductive line,
wherein the second and third conductive lines are on a same side of the gate.
Regarding claim 10, Noguchi teaches in figure 2 and related text that the first and second conductive lines have different lengths (chosen as such) measured in the first direction.
Regarding claim 11, Noguchi teaches in figure 2 and related text that the first nMOS and second pMOS transistors have different conductivity types.
Regarding claim 12, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to have the first and second transistors comprise one or more nanosheets in the device of Noguchi, in order to reduce the size of the devices.
Regarding claims 14 and 19, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to extend the gate across the second and third layers and wraps around the first and second active regions from a cross-sectional view in the in the device of Noguchi, in order to improve the device characteristics by achieving high integration and preventing short channel effects as is well known in the art when using “Gate-All-Around” (GAA) technology.
Regarding claim 15, Noguchi teaches in figure 1 and related text a fifth conductive line 25, 27 in one of the second and third layers, wherein at least one of the first, second, third and fourth conductive lines overlaps the fifth conductive line and is non-overlapped with the gate 20 from a top-view perspective. Noguchi does not teach that the fifth conductive line extending in the second direction. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to extend the fifth conductive line in the second direction, in Noguchi’s device in order to improve the contact resistance of the device by providing larger contact area for external connection.
Regarding claim 16, Noguchi teaches in figure 1 a sixth conductive line 25 arranged in the second layer and electrically connected to the second active region; and a first conductive via electrically connecting the sixth conductive line and the first power rail Vdd.
Regarding claim 17, Noguchi teaches in figure 1 that the sixth/first conductive line is non-overlapped with the first and second conductive lines/gate from a top-view perspective.
Regarding claim 20, Noguchi does not teach that the first power rail has a first width, measured in the first direction, greater than a second width, measured in the first
direction, of the first and second conductive lines.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first power rail has a first width, measured in the first direction, greater than a second width, measured in the first
direction, of the first and second conductive lines, in Noguchi’s device in order to provide more reliable power to the device by having thick power rail.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Noguchi (6,649,980) in view of Lee (2005/0073061).Regarding claim 2, Noguchi teaches substantially the entire structure, as applied to the claims above, except having the gate crosses the first active region and the second active region.
Lee teaches in figure 2 and related text that gate 410 crosses a first active region 130 and a second active region 130.
Lee and Noguchi are analogous art because they are directed to CMOS transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Noguchi because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use the gate crosses the first active region and the second active region in the device of Noguchi, in order to more easily operating the device.
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Noguchi (6,649,980), as applied to the claims above, and further in view of Liaw (2017/0207239).Regarding claims 5 and 8, Noguchi teaches substantially the entire structure, as applied to the claims above, except fifth and sixth conductive lines extending in the third layer and arranged on opposite sides of the first power rail.
Liaw teaches in figure 1 and related text fifth and sixth conductive lines M1 extending in the third layer and arranged on opposite sides of a first rail M1.
Liaw and Noguchi are analogous art because they are directed to vertical transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Noguchi because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use fifth and sixth conductive lines extending in the third layer and arranged on opposite sides of the first power rail in the device of Noguchi, in order to provide better external connections to the device.
Regarding claim 6, Noguchi teaches in figure 1 and related text that the at least one of
the first, second, third and fourth conductive lines overlaps one of the fifth and sixth conductive lines from a top-view perspective.
Regarding claim 7, Noguchi teaches in figure 1 and related text a first 17 conductive via arranged between the first and third layers and electrically connecting the first
conductive line to the fifth conductive line.
Regarding claim 8, in the combined device of Noguchi seventh and eighth conductive lines extending in the fourth layer and arranged on opposite sides of the second power rail.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
9/12/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
Prosecution Insights