DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6.19.2024, 7.22.2025 and 5.27.2026 are being considered by the examiner.
Claim Objections
Claims are objected to because of the following informalities:
In claim 1, “buffer layer is consist of” should read –buffer layer consists of--.
In claim 11, “buffer layer is consist of” should read –buffer layer consists of--.
In claim 17, “the bottom surface” should read –a bottom surface--
Appropriate correction is required.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chittipeddi et al. (US 20010036716 A1).
Regarding claim 1, Chittipeddi discloses a semiconductor structure containing a hybrid bond contact, comprising:
a first hybrid bond contact (44, “copper plug 44”) located in a dielectric layer (31+58), wherein the first hybrid bond contact is made of copper (inverted Fig. 19);
a first top wiring layer (56, “aluminum bond pad 56”) located in the dielectric layer (31+58) and below (inverted Fig. 19) the first hybrid bond contact, wherein the first top wiring layer is made of aluminum;
a first composite buffer layer (55 which comes from 51) located between the first hybrid bond contact and the first top wiring layer, wherein, from a cross-sectional view (and from a bottom to a top direction in inverted Fig. 19), the first composite buffer layer (55) covers (indirectly at least) two sidewalls and a bottom of the first hybrid bond contact (inverted Fig. 19), and the first composite buffer layer is consist of a titanium layer, a titanium nitride layer, a tantalum nitride layer, and a tantalum layer ([0011] – “barrier layer 41 is Ta, TaN, Ti, or TiN, although other materials may be used”, [0013] – “a second barrier layer 51 is blanket deposited over the structure as shown in FIG. 15. This barrier layer has essentially the same prescription as barrier layer 41”, and, claim 1 – “said barrier layer being of a material selected from the group consisting of Ta, TaN, Ti, TiN, and combinations thereof”. A combination consisting of Ta, TaN, Ti, TiN is disclosed which meets the claim).
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Regarding claim 11, Chittipeddi discloses a method for manufacturing a semiconductor structure containing a hybrid bond contact, comprising:
forming a first hybrid bond contact (44, “copper plug 44”) located in a dielectric layer (31+58), wherein the first hybrid bond contact is made of copper (inverted Fig. 19);
forming a first top wiring layer (56, “aluminum bond pad 56”) located in the dielectric layer (31+58) and below (inverted Fig. 19) the first hybrid bond contact, wherein the first top wiring layer is made of aluminum;
forming a first composite buffer layer (55 which comes from 51) located between the first hybrid bond contact and the first top wiring layer, wherein, from a cross-sectional view (and from a bottom to a top direction in inverted Fig. 19), the first composite buffer layer covers (indirectly at least) two sidewalls and a bottom of the first hybrid bond contact (inverted Fig. 19), and the first composite buffer layer (55) is consist of a titanium layer, a titanium nitride layer, a tantalum nitride layer, and a tantalum layer ([0011] – “barrier layer 41 is Ta, TaN, Ti, or TiN, although other materials may be used”, [0013] – “a second barrier layer 51 is blanket deposited over the structure as shown in FIG. 15. This barrier layer has essentially the same prescription as barrier layer 41”, and, claim 1 – “said barrier layer being of a material selected from the group consisting of Ta, TaN, Ti, TiN, and combinations thereof”. A combination consisting of Ta, TaN, Ti, TiN is disclosed which meets the claim).
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Claims 1, 6-7, 11 and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang et al. (US 20110101521 A1).
Regarding claim 1, Hwang discloses a semiconductor structure (Fig. 1H) containing a hybrid bond contact, comprising:
a first hybrid bond contact (22, “The PPI line 22 may include, but not limited to, for example copper”) located in a dielectric layer (10/14/26; 10 comprises dielectrics per [0013]), wherein the first hybrid bond contact is made of copper;
a first top wiring layer (12, “conductive region 12 may include…aluminum”) located in the dielectric layer (10/14/26) and below the first hybrid bond contact, wherein the first top wiring layer is made of aluminum;
a first composite buffer layer (16 which is part of 20; Fig. 1B) located between the first hybrid bond contact (22) and the first top wiring layer (12), wherein, from a cross-sectional view, the first composite buffer layer covers two sidewalls and a bottom of the first hybrid bond contact (Fig. 1B), and the first composite buffer layer is consist of a titanium layer, a titanium nitride layer, a tantalum nitride layer, and a tantalum layer ([0015] – “The adhesion layer 16 may include commonly used barrier materials such as titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof”. A combination consisting of Ti, TiN, Ta, TaN is disclosed which meets the claim).
Regarding claim 6, Hwang discloses the semiconductor structure containing a hybrid bond contact according to claim 1, further comprising a wiring layer ([0013]) located below the first top wiring layer (12), wherein the wiring layer is made of copper ([0013] - “Metal lines in the metallization structure may be formed of copper or copper alloys” and “A contact region 12 is a top metallization layer formed in a top-level inter-layer dielectric layer” implicitly discloses copper wiring lines below layer 12, Fig. 1H).
Regarding claim 7, Hwang discloses the semiconductor structure containing a hybrid bond contact according to claim 1, wherein the first hybrid bond contact (22) includes an upper portion (above 14) and a lower portion (within 14), wherein a width of the upper portion is greater than a width of the lower portion (Fig. 1H), and the first composite buffer layer (16 which is part of 20) covers a bottom surface and two sidewalls of the lower portion (Figs. 1B and 1H).
Regarding claim 11, Hwang discloses a method for manufacturing a semiconductor structure containing a hybrid bond contact, comprising:
forming a first hybrid bond contact (22, “The PPI line 22 may include, but not limited to, for example copper”) located in a dielectric layer (10/14/26; 10 comprises dielectrics per [0013]), wherein the first hybrid bond contact is made of copper (Fig. 1H);
forming a first top wiring layer (12, “conductive region 12 may include…aluminum”) located in the dielectric layer (10/14/26) and below the first hybrid bond contact, wherein the first top wiring layer is made of aluminum;
forming a first composite buffer layer (16 which is part of 20; Fig. 1B) located between the first hybrid bond contact (22) and the first top wiring layer (12), wherein, from a cross-sectional view, the first composite buffer layer covers two sidewalls and a bottom of the first hybrid bond contact (Figs. 1B and 1H), and the first composite buffer layer is consist of a titanium layer, a titanium nitride layer, a tantalum nitride layer, and a tantalum layer ([0015] – “The adhesion layer 16 may include commonly used barrier materials such as titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof”. A combination consisting of Ti, TiN, Ta, TaN is disclosed which meets the claim).
Regarding claim 16, Hwang discloses the method for manufacturing a semiconductor structure containing a hybrid bond contact according to claim 11, further comprising forming a wiring layer ([0013]) located below the first top wiring layer (12), wherein the wiring layer is made of copper ([0013] - “Metal lines in the metallization structure may be formed of copper or copper alloys” and “A contact region 12 is a top metallization layer formed in a top-level inter-layer dielectric layer” implicitly discloses copper wiring lines below layer 12, Fig. 1H).
Regarding claim 17, Hwang discloses the method for manufacturing a semiconductor structure containing a hybrid bond contact according to claim 11, wherein the first hybrid bond contact (22) includes an upper portion (above 14) and a lower portion (within 14), wherein a width of the upper portion is greater than a width of the lower portion (Fig. 1H), and the first composite buffer layer (16 which is part of 20) covers the bottom surface and sidewalls of the lower portion (Figs. 1B and 1H).
Allowable Subject Matter
Claims 2-5, 8-10, 12-15 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art of record fails to suggest or disclose wherein in the first composite buffer layer, the titanium layer, the titanium nitride layer, the tantalum nitride layer, and the tantalum layer are arranged from bottom to top.
Regarding claim 3, the prior art of record fails to suggest or disclose further comprising an aluminum-titanium (TiAl3) layer located between the first composite buffer layer and the first top wiring layer; claims 4-5 depend from claim 3.
Regarding claim 8, the prior art of record fails to suggest or disclose further comprising another buffer layer covering a bottom surface and two sidewalls of the upper portion of the first hybrid bond contact, wherein the another buffer layer is consist of a tantalum layer and a tantalum nitride layer, and does not contain a titanium layer or a titanium nitride layer.
Regarding claim 9, the prior art of record fails to suggest or disclose wherein the first hybrid bond contact, the first top wiring layer, and the first composite buffer layer are located within a first chip, and further comprising a second chip and a third chip, wherein the size of the first chip is larger than that of the second chip and the third chip, and the first chip is bonded to both the second chip and the third chip simultaneously; claim 10 depends from claim 9.
Regarding claim 12, the prior art of record fails to suggest or disclose wherein in the first composite buffer layer, the titanium layer, the titanium nitride layer, the tantalum nitride layer, and the tantalum layer are arranged from bottom to top.
Regarding claim 13, the prior art of record fails to suggest or disclose further comprising forming an aluminum-titanium (TiAl3) layer located between the first composite buffer layer and the first top wiring layer; claims 14-15 depend from claim 13.
Regarding claim 18, the prior art of record fails to suggest or disclose further comprising forming another buffer layer covering a bottom surface and two sidewalls of the upper portion of the first hybrid bond contact, wherein the another buffer layer is consist of a tantalum layer and a tantalum nitride layer, and does not contain a titanium layer or a titanium nitride layer.
Regarding claim 19, the prior art of record fails to suggest or disclose wherein the first hybrid bond contact, the first top wiring layer, and the first composite buffer layer are located within a first chip, and further comprising a second chip and a third chip, wherein the size of the first chip is larger than that of the second chip and the third chip, and the first chip is bonded to both the second chip and the third chip simultaneously; claim 20 depends from claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20060202346 A1 to Shih et al. discloses (Fig. 14) a barrier layer (52) interposed between a copper layer (44, [0045]) and an aluminum layer (50, [0047]).
US 9214428 B2 to Liu et al. discloses a barrier layer (16) interposed between a copper layer (22, “PPI line 22 may include, but not limited to, for example copper”) and an aluminum layer (12, “conductive region 12 may include…aluminum”).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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/Andres Munoz/ Primary Examiner, Art Unit 2818
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