DETAILED ACTION
This Notice is responsive to communication filed on 06/19/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/19/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the gate oxide layer of claim 10, and the metal salicide block layer of claim 12 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11, 13, and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "the gate structure further comprises space layers located on both sides of the gate conductor" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. The terms “the gate structure” and “the gate conductor” are not defined in claim 1, but are defined in claim 10. Therefore, for the purpose of this examination, claim 11 will be treated as being dependent on claim 10, where “the gate structure” and “the gate conductor” have been defined and have antecedence.
Claim 13 includes a product and process in the same claim. A single claim which claims both apparatus and the method steps of using the apparatus is indefinite (See MPEP 2173.05(p)(II), In Re Katz). For the purpose of this examination, claim 13 will be interpreted as follows:
a sidewalls structure, wherein the sidewalls structure comprises two sides of a first structure located on a substrate, and wherein a top surface of the substrate and/or surfaces of sidewalls comprises few cavities or no cavities.
Claim 14 is also rejected as being dependent on claim 13.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 9-11, and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hong et al. (US 6,046,113).
Regarding claim 1, Hong discloses a method of etching for a semiconductor structure having a substrate Fig: 1A: 12, and a first structure (annotated below) located on part of a top surface of the substrate Fig: 1A: 12, wherein two side surfaces of the first structure are configured as sidewalls (annotated below), the method comprising:
a) forming an insulation layer Fig. 1D: 50 to cover the substrate Fig: 1A: 12, the first structure, and the sidewalls (col. 3, lines 59-61);
b) performing a dry etching process to etch a first portion of the insulation layer Fig. 1D: 50 (col. 4, lines 38-49); and
c) performing a wet etching process to etch a remaining portion of the insulation layer Fig. 1D: 50, in order to expose the top surface of the substrate Fig: 1A: 12 (col. 4, lines 38-42,57-59; lines 28-35 teach the protective layer 50 is removed from the inner surface which is the semiconductor layer, the sidewalls, and the gate body without forming another layer of contaminants (lines 66-67)),
d) wherein a thickness of the first portion of the insulation layer Fig. 1D: 50 etched by the dry etching process is greater than a thickness of the remaining portion of insulation layer Fig. 1D: 50 etched by the wet etching process (col. 4, lines 41-46 teaches approx. 75% is etched by the dry etching process), in order to decrease formation of cavity in the substrate Fig: 1A: 12 and/or sidewalls (col. 4, lines 52-52 teaches the anisotropic dry etch will not attack the sidewalls, lines 62-64 teaches the isotropic wet etch being limited will not impair the side walls and other elements).
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Regarding claim 2, Hong discloses the method of claim 1, wherein the thickness of the remaining portion of the insulation layer Fig. 1D: 50 etched by the wet etching process is not greater than 100 angstroms (col. 4, lines 41-44 teaches a range between 5-100 Angstroms, and a target of 50 Angstroms).
Regarding claim 3, Hong discloses the method of claim 1, wherein the thickness of the remaining portion of the insulation layer Fig. 1D: 50 etched by the wet etching process is not less than 25 angstroms (col. 4, lines 41-44 teaches a range between 5-100 Angstroms, and a target of 50 Angstroms).
Regarding claim 4, Hong discloses the method of claim 1, wherein a surface of the substrate Fig: 1A: 12 and/or a surface of sidewalls comprises few cavities or no cavities (col. 4, lines 52-52 teaches the anisotropic dry etch will not attack the sidewalls, lines 62-64 teaches the isotropic wet etch being limited will not impair the side walls and other elements).
Regarding claim 6, Hong discloses the method of claim 1, wherein the insulation layer Fig. 1D: 50 comprises SiO2 material col. 3, lines 62-64).
Regarding claim 9, Hong discloses the method of claim 1, wherein the wet etching process comprises isotropic etching (col. 4, lines 38-39).
Regarding claim 10, Hong discloses the method of claim 1, wherein the first structure (annotated above) is configured as a gate structure (i.e. gate body + gate insulator) having a gate oxide layer Fig. 1D: 18 (gate insulator having a silicon dioxide/insulator material) located on an upper surface of the substrate Fig. 1D: 12, and a gate conductor Fig. 1D: 14 (gate body having polycrystalline silicon/semiconductor material) located on the gate oxide layer Fig. 1D: 18 (col. 2, lines 50-56).
Regarding claim 11, Hong discloses the method of claim 1, wherein the gate structure further comprises spacer layers Fig. 1D: 32 located on both sides of the gate conductor Fig. 1D: 14.
Regarding claim 13, as mentioned above, claim 13 will be interpreted as “a sidewalls structure, wherein the sidewalls structure comprises two sides of a first structure located on a substrate, and wherein a top surface of the substrate and/or surfaces of sidewalls comprises few cavities or no cavities.” Hong discloses a sidewalls structure (annotated), wherein the sidewalls structure comprises two sides of a first structure (two sides annotated) located on a substrate Fig. 1C: 12, and wherein a top surface of the substrate Fig. 1C: 12 and/or surfaces of sidewalls comprises few cavities or no cavities (col. 4, lines 52-52 teaches the anisotropic dry etch will not attack the sidewalls, lines 62-64 teaches the isotropic wet etch being limited will not impair the side walls and other elements).
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Regarding claim 14, Hong discloses a field-effect transistor (col.2, lines 33-35 teaches a narrow linewidth transistor which is a FET), comprising the sidewalls structure of claim 13, and further comprising:
a) the substrate Fig. 1D: 12; and
b) a gate structure Fig. 1D: 14+18 located on part of a top surface of the substrate Fig. 1D: 12,
c) wherein two side surfaces of the gate structure Fig. 1D: 14+18 are configured as the sidewalls structure (annotated above), and a surface of the substrate Fig. 1D: 12 and/or surfaces of sidewalls comprises few cavities or no cavities (col. 4, lines 52-52 teaches the anisotropic dry etch will not attack the sidewalls, lines 62-64 teaches the isotropic wet etch being limited will not impair the side walls and other elements).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference(s).
Claims 5 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 6,046,113) as applied to claim 1 above, and further in view of Thei et al. (US 20100311231).
Regarding claim 5, Thei discloses the following claim limitations not explicitly disclosed by Hong et al.:
the method of claim 1, wherein a total thickness of the insulation layer Fig. 2E: 254 is from 300 angstroms to 800 angstroms (para. 0030 teaches an ILD layer with dielectric material, silicon nitride/oxide in a thickness range of 300 – 500 .ANG. which is within the claimed range).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Hong’s teachings with Thei’s teachings in order to maintain a low dishing and metal erosion effect (para. 0030).
Regarding claim 7, Thei discloses the following claim limitations not explicitly disclosed by Hong et al.:
the method of claim 1, wherein the insulation layer Fig. 2E: 254 comprises two layers of material SiO2 and SiN (para. 0030 teaches ILD layer 254 comprises silicon oxide and silicon nitride material, and comprises one or more dielectric layers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Hong’s teachings with Thei’s teachings in order to provide an insulating layer with more than one dielectric layer to maintain a low dishing and metal erosion effect (para. 0030).
Regarding claim 8, Thei discloses the following claim limitations not explicitly disclosed by Hong et al.:
the method of claim 1, wherein the insulation layer Fig. 2E: 254 comprises three layers of material SiO2, SiN, and SiO2 (para. 0030 teaches ILD layer 254 comprises silicon oxide and silicon nitride material, and comprises one or more dielectric layers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Hong’s teachings with Thei’s teachings in order to provide an insulating layer with more than one dielectric layer to maintain a low dishing and metal erosion effect (para. 0030).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 6,046,113) as applied to claim 1 above, and further in view of Chern (US 20240405015).
Regarding claim 12, Chern discloses the following claim limitations not explicitly disclosed by Hong et al.:
the method of claim 1, wherein the insulation layer Fig. 8b: SBL comprises a metal salicide block layer Fig. 8b: SBL (para. 0046).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Hong’s teachings with Chern’s forming self-aligned silicide layers in order to decrease contact resistance of the guard ring, gates, source and drain regions, and also decrease the resistance of the mentioned elements (para. 0046).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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