DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Booth et al. (US 2008/0233699) (hereafter Booth).
Regarding claim 1, Booth discloses a structure comprising:
a semiconductor substrate 100 (Fig. 3, paragraph 0016);
isolation regions 115 (Fig. 3, paragraph 0016) in the semiconductor substrate 100 (Fig. 3);
a semiconductor fin 140 (Fig. 3, paragraph 0020) protruding higher than top surfaces of the isolation regions 115 (Fig. 3), wherein the isolation regions 115 (Fig. 3) are on opposing sides of the semiconductor fin 140 (Fig. 3);
a dielectric layer (120 and 145A in Fig. 3, paragraph 0033) on a top surface and sidewalls of the semiconductor fin 140 (Fig. 3); and
a capping layer (165 and 170 in Fig. 3, paragraph 0033) comprising :
a top portion (horizontal portion of 165 contacting 145A in Fig. 3) overlying the dielectric layer (120 and 145A in Fig. 3) and overlapping the semiconductor fin 140 (Fig. 3); and
a sidewall portion (vertical portions of 165 in Fig. 3) on a sidewall of at least a top portion of the semiconductor fin 140 (Fig. 3), wherein the sidewall portion (vertical portions of 165 in Fig. 3) is thinner (see Fig. 3, wherein the horizontal length of vertical portions of 165 is thinner than the horizontal length of horizontal portion of 165 contacting 145A) than the top portion (horizontal portion of 165 contacting 145A in Fig. 3); and
a first dielectric feature 150 (Fig. 3, paragraph 0022) contacting an edge of the capping layer (165 and 170 in Fig. 3).
Regarding claim 2, Booth further discloses the structure of claim 1 further comprising a gate stack (155 and 160 in Fig. 3, paragraph 0023) on the semiconductor fin 140 (Fig. 3), wherein a sidewall of the top portion (portions of 165 and 170 higher than the top surface of 145A in Fig. 3) of the capping layer (165 and 170 in Fig. 3) physically contacts (see Fig. 3, wherein 165 contacts 155 and 160) a second sidewall of the gate stack (155 and 160 in Fig. 3).
Regarding claim 3, Booth further discloses the structure of claim 2, wherein the first dielectric feature 150 (Fig. 3) comprises a gate dielectric 150 (Fig. 3) of the gate stack (155 and 160 in Fig. 3).
Regarding claim 4, Booth further discloses the structure of claim 2 further comprising a gate spacer 175 (Fig. 3, paragraph 0025) on a sidewall of the gate stack (155 and 160 in Fig. 3), wherein a first edge of the gate spacer 175 (Fig. 3) is vertically aligned (see Fig. 3, wherein a surface of 175 contacting 160 and a surface of 165 contacting 160 are vertically aligned) to a second edge of the capping layer (165 and 170 in Fig. 3).
Regarding claim 5, Booth further discloses the structure of claim 4, wherein a third edge of the gate spacer 175 (Fig. 3, paragraph 0025) is vertically aligned (see Fig. 3, wherein, at region where 170 and 175 are contacting, an edge of 175 and an edge of 170 are vertically aligned) to a fourth edge of the capping layer (165 and 170 in Fig. 3), and wherein the first edge (edge of 175 contacting 160 in Fig. 3) and the third edge are opposing edges (edge of 175 where 170 and 175 are contacting in Fig. 3) of the gate spacer 175 (Fig. 3).
Regarding claim 6, Booth (utilized different element for a sidewall portion as applied in claim 1 in the above) discloses a structure comprising:
a semiconductor substrate 100 (Fig. 3, paragraph 0016);
isolation regions 115 (Fig. 3, paragraph 0016) in the semiconductor substrate 100 (Fig. 3);
a semiconductor fin 140 (Fig. 3, paragraph 0020) protruding higher than top surfaces of the isolation regions 115 (Fig. 3), wherein the isolation regions 115 (Fig. 3) are on opposing sides of the semiconductor fin 140 (Fig. 3);
a dielectric layer (120 and 145A in Fig. 3, paragraph 0033) on a top surface and sidewalls of the semiconductor fin 140 (Fig. 3); and
a capping layer (165 and 170 in Fig. 3, paragraph 0033) comprising :
a top portion (horizontal portion of 165 contacting 145A in Fig. 3) overlying the dielectric layer (120 and 145A in Fig. 3) and overlapping the semiconductor fin 140 (Fig. 3); and
a sidewall portion (upper vertical portions of 165 in Fig. 3) on a sidewall of at least a top portion of the semiconductor fin 140 (Fig. 3), wherein the sidewall portion (upper vertical portions of 165 in Fig. 3) is thinner (see Fig. 3, wherein the horizontal length of vertical portions of 165 is thinner than the horizontal length of horizontal portion of 165 contacting 145A) than the top portion (horizontal portion of 165 contacting 145A in Fig. 3);
a first dielectric feature 150 (Fig. 3, paragraph 0022) contacting an edge of the capping layer (165 and 170 in Fig. 3); and
wherein the sidewall portion (upper vertical portions of 165 in Fig. 3) of the capping layer (165 and 170 in Fig. 3) comprises a bottom end (bottom surface of upper vertical portions of 165 in Fig. 3) higher than top ends (top surface of 115 in Fig. 3) of the isolation regions 115 (Fig. 3).
Regarding claim 7, Booth further discloses the structure of claim 1, wherein the sidewall portion (vertical portions of 165 in Fig. 3) of the capping layer (165 and 170 in Fig. 3) comprises a bottom end (bottom surface of 165 contacting 115 in Fig. 3) contacting a top surface (top surface of 115 in Fig. 3) of the isolation regions 115 (Fig. 3).
Regarding claim 8, Booth (utilized different elements for a sidewall portion as applied in claim 1 in the above) discloses a structure comprising:
a semiconductor substrate 100 (Fig. 3, paragraph 0016);
isolation regions 115 (Fig. 3, paragraph 0016) in the semiconductor substrate 100 (Fig. 3);
a semiconductor fin 140 (Fig. 3, paragraph 0020) protruding higher than top surfaces of the isolation regions 115 (Fig. 3), wherein the isolation regions 115 (Fig. 3) are on opposing sides of the semiconductor fin 140 (Fig. 3);
a dielectric layer (120 and 145A in Fig. 3, paragraph 0033) on a top surface and sidewalls of the semiconductor fin 140 (Fig. 3); and
a capping layer (165 and 170 in Fig. 3, paragraph 0033) comprising :
a top portion (horizontal portion of 165 contacting 145A in Fig. 3) overlying the dielectric layer (120 and 145A in Fig. 3) and overlapping the semiconductor fin 140 (Fig. 3); and
a sidewall portion (170 and vertical portions of 165 in Fig. 3) on a sidewall of at least a top portion of the semiconductor fin 140 (Fig. 3), wherein the sidewall portion (vertical portions of 165 in Fig. 3) is thinner (see Fig. 3, wherein the horizontal length of vertical portions of 165 is thinner than the horizontal length of horizontal portion of 165 contacting 145A) than the top portion (horizontal portion of 165 contacting 145A in Fig. 3);
a first dielectric feature 150 (Fig. 3, paragraph 0022) contacting an edge of the capping layer (165 and 170 in Fig. 3); and
wherein upper portions of the sidewall portion (170 and vertical portions of 165 in Fig. 3) are increasingly thicker (see Fig. 3, wherein horizontal length of 170 and upper vertical portions of 165 thicker than horizontal length of lower vertical portions of 165) than respective lower portions of the sidewall portion (170 and vertical portions of 165 in Fig. 3).
Regarding claim 9, Booth further discloses the structure of claim 1, wherein the capping layer (165 and 170 in Fig. 3, paragraph 0025, wherein “silicon nitride”) comprises silicon nitride.
Regarding claim 10, Booth further discloses the structure of claim 9, wherein the dielectric layer (120 and 145A in Fig. 3, paragraph 0017, wherein “silicon oxide”) comprises silicon oxide.
Regarding claim 11, Booth discloses a structure comprising:
a protruding structure 140 (Fig. 3, paragraph 0020) protruding higher than features 115 (Fig. 3, paragraph 0016) that are on opposing sides of the protruding structure 140 (Fig. 3), wherein the protruding structure 140 (Fig. 3) comprises a top surface (top surface of 140 in Fig. 3) and sidewall surfaces (sidewall surfaces of 140 in Fig. 3), and wherein the protruding structure comprises: a semiconductor fin 140 (Fig. 3); and
a dielectric layer (150 and 145A in Fig. 3, paragraph 0033) comprising sidewall portions 150 (Fig. 3, paragraph 0033) on sidewall surfaces of the semiconductor fin 140 (Fig. 3), and a first top portion 145A (Fig. 3, paragraph 0033) directly over the top surface of the semiconductor fin 140 (Fig. 3);
a dielectric capping layer (165 and 175 in Fig. 3, paragraph 0033) comprising a second top portion (portion of 165 contacting 145A in Fig. 3) directly over the first top portion 145A (Fig. 3) of the dielectric layer (150 and 145A in Fig. 3); and
a gate spacer 170 (Fig. 3, paragraph 0025), wherein an edge of the gate spacer 170 (Fig. 3) is in contact with the dielectric capping layer (165 and 175 in Fig. 3) and a bottom portion of the dielectric layer (150 and 145A in Fig. 3).
Regarding claim 12, Booth further discloses the structure of claim 11, wherein the first top portion 145A (Fig. 3) of the dielectric layer (150 and 145A in Fig. 3) has a same thickness (see Fig. 3, wherein horizontal length of 145A is same as horizontal length between surfaces of 150 contacting 165) as the sidewall portions 120 (Fig. 3) of the dielectric layer (150 and 145A in Fig. 3).
Regarding claim 13, Booth further discloses the structure of claim 12, wherein the dielectric capping layer (165 and 170 in Fig. 3) comprises an additional sidewall portion (165 and 170 in Fig. 3) on one of the sidewall portions of the dielectric layer (150 and 145A in Fig. 3), and wherein the additional sidewall portion (165 and 170 in Fig. 3) of the dielectric capping layer comprises an upper portion and a lower portion thinner (see Fig. 3, wherein horizontal length of 170 and upper vertical portions of 165 thicker than horizontal length of lower vertical portions of 165) than the upper portion.
Regarding claim 14, Booth further discloses the structure of claim 11, wherein the dielectric capping layer (165 and 170 in Fig. 3, paragraph 0025, wherein “silicon nitride”) has a higher nitrogen atomic percentage than the dielectric layer (150 and 145A in Fig. 3, paragraph 0022, wherein “silicon oxide”).
Regarding claim 15, Booth further discloses the structure of claim 11, wherein the dielectric capping layer (165 and 170 in Fig. 3, paragraph 0025, wherein “silicon nitride”) comprises silicon nitride, and the dielectric layer (150 and 145A in Fig. 3, paragraph 0022, wherein “silicon oxide”) comprises silicon oxide.
Regarding claim 16, Booth further discloses the structure of claim 11 further comprising a gate stack (155 and 160 in Fig. 3, paragraph 0023) on the semiconductor fin 140 (Fig. 3), wherein both of the dielectric layer (150 and 145A in Fig. 3) and the dielectric capping layer (165 and 175 in Fig. 3) contact the gate stack (155 and 160 in Fig. 3).
Regarding claim 17, Booth discloses a structure comprising:
a semiconductor substrate 100 (Fig. 3, paragraph 0016);
isolation regions 115 (Fig. 3, paragraph 0016) extending into the semiconductor substrate 100 (Fig. 3);
a semiconductor fin 140 (Fig. 3, paragraph 0020) protruding higher than top surfaces of the isolation regions 115 (Fig. 3), wherein the isolation regions 115 (Fig. 3) are on opposing sides of the semiconductor fin 140 (Fig. 3);
a dielectric layer (150 and 145A in Fig. 3) on a top surface and sidewalls of the semiconductor fin 140 (Fig. 3);
a dielectric capping layer (165 and 170 in Fig. 3, paragraph 0033) comprising a first portion 165 (Fig. 3) directly over the semiconductor fin 140 (Fig. 3), wherein the dielectric capping layer (165 and 170 in Fig. 3) comprises:
a top portion (horizontal portion of 165 contacting 145A in Fig. 3) overlying the dielectric layer (150 and 145A in Fig. 3), wherein the top portion has a first thickness; and a sidewall portion (upper vertical portion of 165 contacting 150 in Fig. 3) on a sidewall of a top portion of the semiconductor fin 140 (Fig. 3), wherein the sidewall portion (upper vertical portion of 165 contacting 150 in Fig. 3) has a second thickness smaller (see Fig. 3, wherein the horizontal length of upper vertical portion of 165 contacting 150 is smaller than the horizontal length of horizontal portion of 165 contacting 145A) than the first thickness (horizontal portion of 165 contacting 145A in Fig. 3); and
a semiconductor region 180 (Fig. 3, paragraph 0025) contacting a first edge of the dielectric capping layer (165 and 170 in Fig. 3).
Regarding claim 18, Booth further discloses the structure of claim 17 further comprising a gate stack (155 and 160 in Fig. 3, paragraph 0025) on the semiconductor fin 140 (Fig. 3), wherein a second edge of the capping layer (165 and 170 in Fig. 3) physically contacts the gate stack (155 and 160 in Fig. 3).
Regarding claim 19, Booth further discloses the structure of claim 17, wherein opposite edges of the dielectric layer (150 and 145A in Fig. 3) and opposite edges of the dielectric capping layer (165 and 170 in Fig. 3) are vertically aligned (see Fig. 3, wherein surfaces of 150 contacting 165 and surfaces of 165 contacting 150 are vertically aligned).
Regarding claim 20, Booth further discloses the structure of claim 17, wherein a bottom end of the sidewall portion (upper vertical portion of 165 contacting 150 in Fig. 3) of the dielectric capping layer (165 and 170 in Fig. 3) is higher than a respective bottom end of the dielectric layer (150 and 145A in Fig. 3).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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