Prosecution Insights
Last updated: October 02, 2026
Application No. 18/747,849

SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING

Non-Final OA §102§103
Filed
Jun 19, 2024
Priority
Mar 19, 2021 — provisional 63/163,717 +1 more
Examiner
GOODWIN, DAVID J
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
67%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
553 granted / 821 resolved
+7.4% vs TC avg
Strong +16% interview lift
Without
With
+16.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
54 currently pending
Career history
892
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
60.4%
+20.4% vs TC avg
§102
17.8%
-22.2% vs TC avg
§112
18.6%
-21.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 821 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 2, 3, 5, and 9 is/are rejected under 35 U.S.C. 102a2 as being anticipated by Chien (US 2022/0157821) Regarding claim 1. Chien teaches: A semiconductor structure, comprising: a first trench resonator (fig 5:257a; [para 0052]) (note a capacitor inherently has a parasitic self-resonance dependent on the equivalent series resistance, the equivalent series inductance, and the capacitance) in a first dielectric layer (fig 5:137,143; [para 0052]) and comprising a first conductive layer (fig 5:251a; [para 0053]) and a second dielectric layer (fig 5:253a; [para 0053]); and a second trench resonator (fig 7:257b; [para 0054]) in the first dielectric layer (fig 6:137,143; [para 0052])comprising a second conductive layer (fig 6:251b; [para 0054]) and a third dielectric layer (fig 6:253b; [para 0054]), wherein at least one of: a material composition of the second dielectric layer differs from a material composition of the third dielectric layer, or a material composition of the first conductive layer differs from a material composition of the second conductive layer ([para 0055]). Regarding claim 2. Chien teaches the semiconductor structure of claim 1, comprising: a first conductive contact (fig 5:141; [para 0046]) in the first dielectric layer (fig 5:137,143; [para 0052]) and electrically coupled to the first conductive layer (fig 5:251a; [para 0053]); and a first device (fig 5:113b; [para 0044]) electrically coupled to the first conductive contact (fig 5:141; [para 0046]) such that the first device (fig 5:113b; [para 0044]) is electrically coupled to the first conductive layer (fig 5:251a; [para 0053]) through the first conductive contact (fig 5:141; [para 0046]). Regarding claim 3. Chien teaches the semiconductor structure of claim 2, comprising: a second conductive contact (fig 6:141; [para 0052]) in the first dielectric layer (fig 5:137,143; [para 0052]) and electrically coupled to the second conductive layer (fig 6:251b; [para 0054]); and a second device (fig 6:113b; [para 0052]) electrically coupled to the second conductive contact (fig 6:141; [para 0052]) such that the second device (fig 6:113b; [para 0052]) is electrically coupled to the second conductive layer (fig 6:251b; [para 0054]) through the first conductive contact (fig 6:141; [para 0052]). Regarding claim 5. Chien teaches the semiconductor structure of claim 1, wherein a top surface of the first conductive layer (fig 5:251a; [para 0053]) is co-planar with a top surface of the second dielectric layer (fig 5:253a; [para 0053]). Regarding claim 9. Chien teaches the semiconductor structure of claim 1, a conductive contact (fig 5:141; [para 0046]) in the first dielectric layer (fig 5:137,143; [para 0052]) and electrically coupled to the first conductive layer (fig 5:251a; [para 0053]). Claim(s) 16 and 19 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Kim (US 2002/0185671) Regarding claim 16 Kim teaches: A semiconductor structure, comprising: a first conductive contact (fig 1f:13; [para 0023]) in a first dielectric layer (fig 1f:12,15,17,18; [para 0024]); and a first trench resonator (fig 1f:27; [para 0028])(note a capacitor inherently has a parasitic self-resonance dependent on the equivalent series resistance, the equivalent series inductance, and the capacitance)in the first dielectric layer (fig 1f:12,15,17,18; [para 0024]), wherein the first trench resonator (fig 1f:27; [para 0028]) comprises: a first barrier layer (fig 1f:20; [para 0028]) in contact with the first conductive contact (fig 1f:13; [para 0023]); a first conductive layer (fig 1f:21a; [para 0028]) overlying the first barrier layer (fig 1f:20; [para 0028]); and a second dielectric layer (fig 1f:22a; [para 0028]) overlying the first conductive layer (fig 1f:20; [para 0028]). Regarding claim 19. Kim teaches the semiconductor structure of claim 16, Kim teaches: a top surface of the first conductive layer (fig 1f:20; [para 0028]) is co-planar with a top surface of the first dielectric layer (fig 1f:12,15,17,18; [para 0024]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s). Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chien (US 2022/0157821) as applied to claim 1 and further in view of Ching (US 2010/0213572) Regarding claim 6. Chien teaches the semiconductor structure of claim 1, above Chen does not teach a fourth dielectric. Ching teaches: a fourth dielectric layer (fig 1:17; [para 0014]) overlying the second dielectric layer (fig 1:230; [para 0018]); and a conductive pad (fig 1:m1; [para 0015]) overlying the fourth dielectric layer (fig 1:17; [para 0014]) and the second dielectric layer (fig 1:230; [para 0018]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a fourth dielectric and conductive pad in order to provide a voltage supply to the devices. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chien (US 2022/0157821) as applied to claim 9 above, and further in view of Kim (US 2004/0232557) Regarding claim 10. Chien teaches the semiconductor structure of claim 9, Chien does not teach a barrier layer Kim teaches: the first trench resonator (fig 1f:27; [para 0028]) comprises a barrier layer (fig 1f:20; [para 0028]) between the first conductive layer (fig 1f:2021a; [para 0028]) and the first dielectric layer (fig 1f:15,17; [para 0025.0027]), and the conductive contact (fig 1f:13; [para 0027]) is in contact with the barrier layer (fig 1f:20; [para 0028]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a barrier layer in order to prevent diffusion of the electrode material into the surrounding dielectric (paragraph 13). Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chien (US 2022/0157821) as applied to claim 1 and further in view of Ching (US 2010/0213572) Regarding claim 11. Chien teaches the semiconductor structure of claim 1, Chien does not teach: a conductive pad overlying the second dielectric layer Ching teaches: a conductive pad (fig 1:M1; [para 0015]) overlying the second dielectric layer (fig 1:230; [para 0018]) and a portion of the first conductive layer (fig 1:222; [para 0018]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a conductive pad over the dielectric in order to conduct voltage to the devices. Claim(s) 12 through 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chien (US 2022/0157821) in view of Shih (US 2021/0343735). Regarding claim 12 Chien teaches: A semiconductor structure, comprising: a first die region having a functional region (fig 4:200; [para 0051]) ; , comprising: a first trench resonator (fig 5:257a; [para 0052]) comprising a first conductive layer (fig 5:251a; [para 0053]) and a first dielectric layer (fig 5:253a; [para 0052]); and a second trench resonator (fig 7:257b; [para 0054]) comprising a second conductive layer (fig 6:251b; [para 0054]) and a second dielectric layer (fig 6:253b; [para 0054]), wherein a material composition (silicon dioxide; [para 0055]) of the first dielectric layer(fig 5:253a; [para 0052]) differs from a material composition (hafnium dioxide; [para 0055]) of the second dielectric layer (fig 6:253b; [para 0054]) . Chien does not teach a peripheral region having a monitor structure therein. Shih teaches A semiconductor structure, comprising: a first die region (fig 1,24:100; [para 0014])having a functional region (fig 1,24:104c; [para 0014]) and a peripheral region ([fig 1,24:104t; [para 0014,0020]) outside the functional region (fig 1,24:104c; [para 0014]); and a first monitoring structure (fig 1,24:112,134’; [para 0014,0020]) in the peripheral region ([fig 1,24:104t; [para 0014,0020]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide memory structures in the peripheral region in order to enable testing of the structure (paragraph 0013). Regarding claim 13 Chien in view of Shih teaches the semiconductor structure of claim 12, Chien teaches: comprising: a second structure in the functional region (fig 4:200; [para 0051]), comprising: a third trench resonator (fig 4,5:257a; [para 0052]); and a fourth trench resonator (fig 4,5:257a; [para 0052]). Shih teaches: a second monitoring structure (fig 1,3:112; [para 0028,0020]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide additional structures to test additional areas. In reHarza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). MPEP 2144.VI.B. Regarding claim 14. Chien in view of Shih teaches the semiconductor structure of claim 12, Chien teaches: a second structure (fig 4:200; [para 0051]) , comprising: a third trench resonator (fig 4,5:257a; [para 0052]); and a fourth trench resonator. (fig 4,5:257a; [para 0052]). Shih teaches: a second monitoring structure in (fig 1,3:112; [para 0028,0020]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide additional structures to test additional areas, gain additional data, and increase redundancy. In reHarza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). MPEP 2144.VI.B. Regarding claim 15. Chien in view of Shih teaches the semiconductor structure of claim 15, Shih teaches: a dummy pattern (fig 15:144’; [para 0024]) disposed between the first monitoring structure (fig 15,20:134’; [para 0020]) and the second monitoring structure (fig 15,20:134’; [para 0020]). Claim(s) 17, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2002/0185671) as applied to claim 16 and further in view of Giraudin (US 2006/0234464) Regarding claim 17. Kim teaches the semiconductor structure of claim 16, Kim does not teach a third dielectric Giraudin teaches: a third dielectric layer (fig 8:2d; [para 0027]) overlying the first trench resonator (fig 8:4a,4b,4c; [para 0020]) and in contact with the first conductive layer (fig 8:4b; [para 0020]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a third dielectric layer I order to cover the semiconductor structures thereby providing protection and support for subsequent features. Regarding claim 18. Kim in view of Giraudin teaches the semiconductor structure of claim 17, Giraudin teaches: the third dielectric layer (fig 8:2d; [para 0027]) is in contact with the first conductive contact (fig 8:va-vd; [para 0023]). Regarding claim 20. Kim in view of Giraudin teaches the semiconductor structure of claim 16, Giraudin teaches: a third dielectric layer (fig 8:2d; [para 0027]) overlying the first trench resonator (fig 8:4a,4b,4c; [para 0020]); and a conductive pad (fig 8:10b; [para 0027]) overlying the third dielectric layer (fig 8:2d; [para 0027]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a third dielectric layer I order to cover the semiconductor structures thereby providing protection and support for subsequent features. Allowable Subject Matter Claims 4, 7, and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 4, the prior art does not teach in combination with other elements of the claim, a semiconductor structure, comprising: a first trench resonator in a first dielectric layer and comprising a first conductive layer and a second dielectric layer; and a second trench resonator in the first dielectric layer and comprising a second conductive layer and a third dielectric layer, wherein at least one of: a material composition of the second dielectric layer differs from a material composition of the third dielectric layer, or a material composition of the first conductive layer differs from a material composition of the second conductive layer, the first device comprises a first transistor having a first gate dielectric layer with a first thickness; and the second device comprises a second transistor having a second gate dielectric layer with a second thickness different than the first thickness. Regarding claim 7, the prior art does not teach in combination with other elements of the claim a semiconductor structure, comprising: a first trench resonator in a first dielectric layer and comprising a first conductive layer and a second dielectric layer; and a second trench resonator in the first dielectric layer and comprising a second conductive layer and a third dielectric layer, wherein at least one of: a material composition of the second dielectric layer differs from a material composition of the third dielectric layer, or a material composition of the first conductive layer differs from a material composition of the second conductive layer, the first trench resonator and the second trench resonator are positioned in a scribe line of a semiconductor wafer. Regarding claim 7, the prior art does not teach in combination with other elements of the claim, a semiconductor structure, comprising: a first trench resonator in a first dielectric layer and comprising a first conductive layer and a second dielectric layer; and a second trench resonator in the first dielectric layer and comprising a second conductive layer and a third dielectric layer, wherein at least one of: a material composition of the second dielectric layer differs from a material composition of the third dielectric layer, or a material composition of the first conductive layer differs from a material composition of the second conductive layer, wherein a depth of the first conductive layer, measured from a top surface of the first dielectric layer to a bottommost point of the first conductive layer, is different than a depth of the second conductive layer, measured from the top surface of the first dielectric layer to a bottommost point of the second conductive layer. Regarding claim 12, the prior art does not teach in combination with other elements of the claim, a semiconductor structure, comprising: a first monitoring structure in the peripheral region, comprising: a first trench resonator comprising a first conductive layer and a first dielectric layer; and a second trench resonator comprising a second conductive layer and a second dielectric layer, wherein a material composition of the first dielectric layer differs from a material composition of the second dielectric layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.J.G/Examiner, Art Unit 2817 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Jun 19, 2024
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
67%
Grant Probability
84%
With Interview (+16.5%)
3y 2m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 821 resolved cases by this examiner. Grant probability derived from career allowance rate.

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