DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/24/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 19-20 are objected to because of the following informalities: the typographical error “The method of claim 15” in line 1 is believed to be meant to read as “The method of claim 16”. Appropriate correction is required.
In Re claim 20, it is objected to due its dependence from claim 19.
Allowable Subject Matter
Claims 7; 15; and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
A. Re claim 7, the prior art does not disclose the limitation(s) of: wherein the at least one contact structure has a p-type work function and the at least one polishing resistance material has an n-type work function, in combination with the additionally claimed features of claim 1.
B. Re claim 15, the prior art does not disclose the limitation(s) of: wherein the at least one polishing resistance material has an n-type work function and is laterally spaced apart from the first and second contact structures, respectively, by part of the dummy layer, in combination with the additionally claimed features of claim 9.
C. Re claim 17, the prior art does not disclose the limitation(s) of: wherein the first and second contact structures have a p-type work function and the at least one polishing resistance material has an n-type work function and is laterally spaced apart from the first and second contact structures, respectively, by part of the dummy layer, in combination with the additionally claimed features of claim 16.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiu et al (US 2011/0073957 A1-IDS prior art, hereafter Chiu).
Re claim 1, Chiu discloses in FIG. 6 a semiconductor device, comprising:
a metal thin film (26; ¶ [0016]) disposed on a semiconductor substrate (Si 12; ¶ [0015]), wherein the metal thin film (26) is formed of a metal material selected from a group comprising at least one of: titanium (Ti; [0016]), tantalum (Ta; [0016]), titanium nitride (TiN; [0016]), tantalum nitride (TaN), tungsten (W; [0016]) and tungsten nitride (WN; [0016]);
at least one contact structure (leftmost primary resistance structure 86; ¶ [0024]) disposed on the metal thin film (26), a dummy layer (combination of middle secondary resistance structures 88/portions 28; ¶ [0024] and [0028]) disposed on the metal thin film (26), wherein the dummy layer (88/28) comprises at least one polishing resistance material (TiAl 88; [0024]); and
a transistor gate structure (66; [0024]) disposed adjacent to (near) the at least one contact structure (leftmost primary resistance structure 86),
wherein the at least one contact structure (leftmost primary resistance structure 86), the metal thin film (26) and the transistor gate structure (66) are concurrently formed (as part of a method for integrating a resistor and a metal gate transistor in FIGS. 1-6; [0011]), and wherein a material (TiAl; [0024]) of the transistor gate structure (66) is the same ([0024]) as the at least one polishing resistance material (TiAl 88).
Re claim 2, Chiu discloses the device of claim 1, wherein the at least one polishing resistance material (88) is selected from a group c consisting of a metal-based material (Al, W, TiAl or CoWP; ¶ [0024]), an oxide-based material, a ceramic-based material, and a combination thereof.
Re claim 3 and 4, Chiu discloses the device of claim 1, wherein the at least one polishing resistance material (88) further comprises a barrier material (Ti when 88 is composed of TiAl; ¶ [0024]); and wherein the barrier material is selected from a group consisting of: titanium (Ti; ¶ [0024]), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and a combination thereof.
Re claim 5, Chiu discloses the device of claim 1, wherein the metal thin film (26), and the at least one contact structure contact structure (leftmost 86) form a thin film resistor (¶ [0024]).
Re claim 6, Chiu discloses the device of claim 1, wherein the dummy layer (combination of middle secondary resistance structures 88/portions 28) is formed of a polysilicon material (¶ [0024]).
Re claim 8, Chiu discloses the device of claim 1, wherein the at least one polishing resistance material (88) directly contacts (physically touches) part (region directly under) of the metal thin film (26).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-14; 16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over CHUANG et al (US 2013/0140641 A1-IDS prior, hereafter Chuang) in view of Chiu et al (US 2011/0073957 A1-IDS prior art, hereafter Chiu).
Re claim 9, Chuang discloses in FIG. 3F (with references to FIGS. 3A-3E) a semiconductor device (200), comprising:
a semiconductor substrate (Si 202; [0027]);
a first transistor (306p; [0029]-[0030]) disposed in a first region (200b; [0029]) of the semiconductor substrate (Si 202);
a second transistor (306n; [0029]-[0030]) disposed in the first region (200b) of the semiconductor substrate (Si 202), wherein the first (306p) and second (306n) transistors each has a respective metal gate (218p/218n; [0041] and [0045];
a thin film resistor (200r; ¶ [0042]) disposed in a second region (200a; [0015]) of the semiconductor substrate (Si 202) adjacent to (near) the first region (200b), the thin film resistor (200r) comprising:
a thin film disposed (TiN 214; [0033]) on the semiconductor substrate (Si 202);
first (right 218p) and second (left 218p) contact structures ([0042]) disposed on respective ends (left/right edges) of the thin film (TiN 214);
a dummy layer (216; [0034]) disposed on the thin film (TiN 214) and laterally (left-to-right) between the first (right 218p) and second (left 218p) contact structures; and
a transistor gate structure (214/218p of 306p; [0033] and [0041]) disposed adjacent to the first contact structure (right 218p), wherein the first (right 218p) and second (left 218p) contact structure, the thin film (TiN 214) and the transistor gate structure (218p of 306p) are concurrently formed (as a method in FIGS. 3B-3D; [0009]), and
wherein the metal gate (218p) of the first transistor (306p) includes a metal layer (TiN or TaN; ¶ [0041]) with a work function greater than 5.2 eV (as evidenced by Thei et al, US 2010/0311231 A1-IDS prior art: ¶ [0039] and [0042]), and the metal gate (218n) of the second transistor (306n) includes a metal layer (TiAl or TiAlN; ¶ [0045]) with a work function less than 4.2 eV (as evidenced by Thei et al, US 2010/0311231 A1-IDS prior art: ¶ [0039] and [0042]).
Chuang fails to disclose wherein the dummy layer (216) comprises at least one recessed region at least partially filled with a polishing resistance material.
However,
Chiu discloses in FIG. 6 a semiconductor device, comprising: a dummy layer (combination of middle secondary resistance structures 88/portions 28; ¶ [0024] and [0028]) disposed on a metal thin film (26; [0024]), wherein the dummy layer (88/28) at least one recessed region (54; [0024]) at least partially filled with a polishing resistance material (TiAl 88; [0024]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Chuang, by adding the at least one recessed region at least partially filled with a polishing resistance material, as disclosed by Chiu, which provides heat dissipating ability of the device substantially while reducing voltage coefficient and temperature coefficient of the resistor (Chiu; [0024]).
Re claim 10, Chuang discloses the device of claim 9.
But, fails to disclose wherein a material of the transistor gate structure is the same as the polishing resistance material, and the polishing resistance material comprises at least one of: a metal-based material, an oxide-based material, a ceramic-based material, and a combination thereof.
However, Chiu would render these limitations obvious as disclosed for the transistor gate structure and the polishing resistance material of claims 1-2 above, as would be part of the heat dissipating structures of Chiu discussed for claim 9.
Re claim 11, Chaung discloses the device of claim 9, wherein the thin film (214) is formed of a metal material selected from a group comprising at least one of: titanium (Ti), tantalum (Ta), titanium nitride (TiN; [0042]), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and a combination thereof.
Re claim 12, Chaung discloses the device of claim 9, wherein the dummy layer (216) is formed of a polysilicon material (doped poly-silicon; [0042]).
Re claim 13, Chaung discloses the device of claim 9, wherein the first (200a) and second (200b) regions are laterally (left-to-right) spaced apart from each other by an isolation feature (204b; [0029]).
Re claim 14, Chaung discloses the device of claim 9, wherein the first (right 218p) and second (left 218p) contact structures have a p-type work function ([0041]).
Re claim 16, Chuang discloses in FIGS. 3A-3F a method, comprising:
forming a metal thin film (TiN 214 in FIG. 3B; [0033]) on a semiconductor substrate (Si 202; [0027]);
forming two contact structures (right/left 218p in FIG. 3D; [0042]) on respective ends (right/left edges) of the metal thin film (TiN 214), wherein the two contact structures (right/left 218p) are laterally (left-to-right) spaced from each other by a dummy layer (216; [0034]); and
forming a transistor gate structure (214/218p of 306p; [0033] and [0041]) disposed adjacent to the first contact structure (right 218p), wherein the two contact structures (right/left 218p), the metal thin film (TiN 214) and the transistor gate structure (218p of 306p) are concurrently formed (as a method in FIGS. 3B-3D; [0009]),
wherein the two contact structures (right/left 218p) comprises first (right) and second (left) contact structures ([0042]), and
wherein the forming two contact structures (right/left 218p) on respective ends (right/left edges) of the metal thin film (TiN 214) comprises concurrently forming a p-type metal gate (214/218p of 306p; [0033] and [0041]) for a p-type first field-effect transistor (FET; 306p; [0033] and [0041]) in a transistor region (306p/300p; [0030]) on the semiconductor substrate (Si 202).
Chuang fails to disclose forming a recessed region in the dummy layer, wherein the recessed region is laterally spaced apart from the two contact structures; and filling the recessed region with a polishing resistance material, wherein the dummy layer and the polishing resistance material are disposed on the metal thin film.
However,
Chiu discloses in FIGS. 1-6 ([0023]-[0028]) a method, comprising: forming a recessed region in the dummy layer, wherein the recessed region is laterally spaced apart from two contact structures; and filling the recessed region with a polishing resistance material, wherein the dummy layer and the polishing resistance material are disposed on the metal thin film (see claims 1; and 9).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Chuang, by using the forming a recessed region in the dummy layer, wherein the recessed region is laterally spaced apart from two contact structures; and the filling the recessed region with a polishing resistance material, wherein the dummy layer and the polishing resistance material are disposed on the metal thin film, as disclosed by Chiu, to provide heat dissipating ability of the device substantially while reducing voltage coefficient and temperature coefficient of the resistor (Chiu; [0024]).
Re claims 18-19, Chuang discloses the method of claim 16.
But, fails to disclose wherein the filling the recessed region with a polishing resistance material comprises concurrently forming an n-type metal gate for an n-type first field-effect transistor (FET) in a transistor region on the semiconductor substrate; and wherein a material of the transistor gate structure is the same as the at least one polishing resistance material.
However, Chiu discloses filling the recessed region with a polishing resistance material (88; [0024]) comprises concurrently forming an n-type metal gate (66; [0024]) for an n-type first field-effect transistor (FET; [0016] and [0031]) or a p-type metal gate (66; [0024]) for a p-type first field-effect transistor (FET; [0016] and [0031]) in a transistor region (16; [0015]) on a semiconductor substrate (Si 12; [0015]); and wherein a material (TiAl; [0024]) of the transistor gate structures (66) is the same as the at least one polishing resistance material (88), as would be part of providing heat dissipating ability of a complimentary device (e.g. CMOS) substantially while reducing voltage coefficient and temperature coefficient of the resistor (Chiu; [0024]).
Re claim 20, Chuang discloses the method of claim 19.
But, fails to disclose wherein the material of the transistor gate structure and the polishing resistance material comprises at least one of: a metal-based material, an oxide-based material, a ceramic-based material, and a combination thereof.
However, Chiu would render these limitations obvious as disclosed for the transistor gate structure and the polishing resistance material of claims 1-2 above, as would be part of the heat dissipating structures of Chiu discussed for claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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