Prosecution Insights
Last updated: August 17, 2026
Application No. 18/748,250

CONTACT AND VIA STRUCTURES

Non-Final OA §102§103§112
Filed
Jun 20, 2024
Priority
Aug 30, 2021 — divisional of 12/046,646
Examiner
LEBENTRITT, MICHAEL
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
928 granted / 1007 resolved
+32.2% vs TC avg
Moderate +6% lift
Without
With
+6.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
20 currently pending
Career history
1026
Total Applications
across all art units

Statute-Specific Performance

§101
6.9%
-33.1% vs TC avg
§103
41.4%
+1.4% vs TC avg
§102
28.6%
-11.4% vs TC avg
§112
9.0%
-31.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1007 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 06/20/2024 was filed before the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 17-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. In claim 17, line 5, recites the limitation of forming a sacrificial layer in the first trench. Examiner was unable to locate the “sacrificial layer” in the specification or either the drawings. While, it is conventionally done in the art prior to etching but it is not positively recited within the specification. Paragraph 12 does reference a “layer” is formed and subsequently removed after etching but this is in regards to the formation of the Fin structure (104). Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The term “more vertical” in claim 17 is a relative term which renders the claim indefinite. The term “more vertical” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 11 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shiao et al, US 20160351669 A1. Shiao teaches: 1. A method, comprising: receiving a semiconductor workpiece having a first conductive feature (104a) and a second conductor feature (104b) each embedded within a dielectric layer (106) and adjacent to each other; forming a first trench (306a, 308a) on the first conductive feature (104a) and a second trench (306b, 308b) on the second conductive feature (104b), the first trench (306a, 308a) and the second trench (306b, 308b) having different sidewall profiles (figure 4a); and depositing to form a third conductive feature (142) in the first trench (306a, 308a) and a fourth conductive feature (142) in the second trench (306b, 308b), wherein the forming of the first trench (306a, 308a) and the second trench (306b, 308b) includes etching to modify a first sidewall (figure 4a) of the first trench (306a, 308a). (para 054-056) See figure 4a-4b 2. The method of claim 1, wherein the forming of the first trench (306a, 308a) and the second trench (306b, 308b) includes: etching to form a first initial trench and a second initial trench (figure 3I-3L); and etching to form an extension feature (top portion 142) on the first sidewall of the first initial trench, the extension feature (top portion 142) reaching over the second conductive feature without reaching the second trench. (Figure 4b) 11. A method, comprising: receiving a semiconductor workpiece having a first source/drain feature (104a) and a second source/drain feature (104b) each embedded within a dielectric layer (106, 110, 112) and adjacent to each other; forming a first trench (306a, 308a) and a second trench (306b, 308b) in the dielectric layer (106,110, 112), the first trench exposes a top surface of the first source/drain feature (104a) and the second trench exposes a top surface of the second source/drain feature (104b); modifying the first trench (306a,308a) in the dielectric layer to laterally extend a top portion (308a) of the first trench towards the second trench; and depositing metal fill layers (para 067) in the modified first trench and in the second trench to form first and second source/drain contacts (142), respectively. 12. The method of claim 11, wherein before the modifying of the first trench (306a, 308a), the first and the second trench are formed by a same etching operation. Para 051, figure 3k-3l Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 6-8 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiao (cited above) Shiao fails to teach: 6. The method of claim 1, wherein the etching to modify the first sidewall of the first trench does not modify a second sidewall of the first trench. 7. The method of claim 1, wherein the etching to modify the first sidewall decreases a slope of the first sidewall for at least an upper portion of the first sidewall. 8. The method of claim 1, wherein the etching to modify the first sidewall increases a slope of the first sidewall. 14. The method of claim 11, wherein the modified first trench has a first sidewall and a second sidewall, wherein the first sidewall has a first slope, the second sidewall has a second slope different from the first slope, wherein the second sidewall is a sidewall of the top portion of the first trench. In regards to claims 6-8 and 14, Shiao teaches: Therefore, by changing the ratio of the carbon to fluorine (C/F), the etch rate is adjusted. CF.sub.4+SiO.sub.2.fwdarw.SiF.sub.4(g)+CO.sub.2(g)  (I) [0049] In some embodiments, when tetrafluoromethane (CF.sub.4) is used as a main etch gas in the first etching process 310, the other fluorine-containing gas, such as octofluorocyclobutane (C.sub.4F.sub.8) is used to adjust the ratio of the carbon to fluorine (C/F). In some embodiments, the ratio (C/F) of the carbon to fluorine in the second etching process 330 is controlled to within a range from about 1/4 to about 1/2. In regards to not modifying the second sidewall, one of ordinary skill in the art would of easily used masking materials, such as a hard mask to prevent etching on either side of the trench. Therefore, it would have been obvious to one of ordinary skill in the art to use masks to prevent etching of either side of the trench and to also adjust the chemical ratio to adjust the etch to increase or decrease the profile of the sidewalls (of the trench). Claim(s) 17-20 (as interpreted by Examiner) is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiao (cited above) Shiao teaches: 17. A method, comprising: receiving a semiconductor workpiece having a first source/drain feature (104a) and a second source/drain feature (104b) each embedded within a dielectric layer (106, 110, 112) and adjacent to each other; forming a first trench (306a, 308a) exposing a top surface of the first source/drain feature; forming a masking layer (116), the masking layer (116) having a first opening directly above the first source/drain feature (104a) and a second opening directly above the second source/drain feature (104b); performing an etching process to etch through the first and the second openings by using the masking layer as an etch mask, the etching process etches through the dielectric layer to form a first source/drain contact trench exposing the first source/drain feature and a second source/drain contact trench exposing the second source/drain feature; (figures 3I-3L) para 054-57; and depositing metal fill layers (para 67) in the extended first source/drain contact trench (308) and in the second source/drain contact trench to form first and second source/drain contacts (142), respectively. See Figures 3i-4b Shiao fails to teach: forming a sacrificial layer in the first trench and over the dielectric layer; removing the sacrificial layer to laterally extend the first source/drain contact trench towards the second source/drain contact trench. In regards to theses limitations, Examiner takes official notice that it is well known in the art to form a sacrificial layer prior to etching to prevent overshoot. 19. The method of claim 17, wherein the forming of the first trench includes exposing a sidewall surface of the first source/drain feature. (figures 3i -4b) Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiao as applied to claim 1 above, and further in view of Kim et al, US 2017/ 0213826 A1. Shiao fails to teach: 5. The method of claim 1, wherein the forming of the first trench includes forming the first trench with a plurality of steps on the first sidewall, and wherein the etching to modify the first sidewall of the first trench includes conducting a plurality of etching operations, each etching operation producing a step of the plurality of steps. Kim teaches: [0340] Referring to FIGS. 13 and 14, in the semiconductor device according to some embodiments, a sidewall portion 321s of a third work function control layer 321 may include a first portion 321sa on a bottom portion 321b of the third work function control layer 321 and a second portion 321sb. [0341] The second portion 321sb of the sidewall portion 321s of the third work function control layer 321 may be located farther away from an upper surface of a substrate 100 than the first portion 321sa of the sidewall portion 321s of the third work function control layer 321. [0342] A width t322 of the second portion 321sb of the sidewall portion 321s of the third work function control layer 321 may be different from a width t321 of the first portion 321sa of the sidewall portion 321s of the third work function control layer 321. [0343] For example, the width t321 of the first portion 321sa of the sidewall portion 321s of the third work function control layer 321 may be greater than the width t322 of the second portion 321sb of the sidewall portion 321s of the third work function control layer 321. [0344] In addition, the width t321 of the first portion 321sa of the sidewall portion 321s of the third work function control layer 321 may be substantially equal to a thickness t32 of the third work function control layer 321. For example, the width t322 of the second portion 321sb of the sidewall portion 321s of the third work function control layer 321 may be smaller than the thickness t32 of the third work function control layer 321. [0345] The third work function control layer 321 may include a plurality of third inclined surfaces 321i having acute angles with respect to a sidewall of a third trench 340t. For example, the third work function control layer 321 extending along a sidewall of the third trench 340t may include a plurality of third inclined surfaces 321i having acute angles with respect to the sidewall of the third trench 340t. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim with the primary reference of Shiao, because the width and height of the sidewall can be controlled by changing the etch chemistry and using masks. Allowable Subject Matter Claims 3-4, 9-10, 13, 15, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art references fail to teach: 3. The method of claim 1, wherein the forming of the first trench and the second trench includes: etching to form a first initial trench exposing a portion of the first conductive feature, the first initial trench having the first sidewall with a first slope and a second sidewall with a second slope; forming a masking element in the first initial trench and over the dielectric layer, the masking element have exposed openings vertically above the first conductive feature and the second conductive feature; and etching through the openings of the masking element to modify the first sidewall to having a third slope greater than the second slope and to form the second trench having a third sidewall with the third slope. 9. The method of claim 1, further comprising forming a fifth conductive feature partially embedded within the third conductive feature, wherein the forming of the fifth conductive feature includes: forming a second dielectric layer over the third and the fourth conductive features; etching the second dielectric layer through a masking element to reach and expose a top surface of the third conductive feature; etching the third conductive feature from the exposed top surface of the third conductive feature to form a third trench; and depositing a conductive material into the third trench. 13. The method of claim 11, wherein the extended top portion of the first trench is directly above the second source/drain feature. 15. The method of claim 14, further comprising: forming a second dielectric layer over the first and the second source/drain contacts; etching the second dielectric layer through a masking element to form a source/drain trench that exposes a top surface of the first source/drain contact; partially etching the first source/drain contact to form a modified source/drain trench; and depositing a conductive material in the modified source/drain trench to form a source/drain via. 18. The method of claim 17, wherein the first trench is formed with sidewalls having first slopes, the first and the second source/drain contact trenches are formed with sidewalls having second slopes, and the second slopes are more vertical than the first slopes. 20. The method of claim 17, further comprising: forming a second dielectric layer over the first and the second source/drain contacts; etching the second dielectric layer through a masking element to form a via trench that exposes a top surface of the first source/drain contact; partially etching the exposed first source/drain contact to form a modified via trench; and depositing a conductive material in the modified via trench to form a source/drain via. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lin et al , US 20210074819 A1 teaches: . A semiconductor structure includes a first epitaxial source/drain (S/D) feature disposed over a first semiconductor fin, a second epitaxial S/D feature disposed over a second semiconductor fin and adjacent to the first epitaxial S/D feature, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, a dielectric feature disposed In the ILD layer and contacting the second epitaxial S/D feature, and a conductive feature disposed in the ILD layer and contacting the first epitaxial S/D feature, where a portion of the conductive feature extends to contact the dielectric feature. Tsai et al, US 20190006231 A1 An interconnect structure and a method of forming are provided. The method includes forming an opening in a dielectric layer and an etch stop layer, wherein the opening extends only partially through the etch stop layer. The method also includes creating a vacuum environment around the device. After creating the vacuum environment around the device, the method includes etching through the etch stop layer to extend the opening and expose a first conductive feature. The method also includes forming a second conductive feature in the opening. CHANEMOUGAME D et al, US 10374040 teaches: Abstract NOVELTY - The semiconductor device has a source/drain region disposed over a semiconductor material layer. An interconnect structure is disposed over and in electrical contact with the source/drain region. The interconnect structure includes a conductive liner disposed over the source/drain region and a conductive fill layer disposed over the conductive liner. The interconnect structure has a reentrant profile in which a horizontal critical dimension in an upper portion of the interconnect structure is smaller than a horizontal critical dimension in a lower portion of the interconnect structure. A conductive contact (950) is disposed over the interconnect structure and in direct physical contact with the sidewalls of the interconnect structure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MICHAEL . LEBENTRITT Primary Examiner Art Unit 2893 /MICHAEL LEBENTRITT/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jun 20, 2024
Application Filed
Jul 21, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
98%
With Interview (+6.3%)
2y 3m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1007 resolved cases by this examiner. Grant probability derived from career allowance rate.

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