DETAILED ACTION
This action is responsive to the following communications: the Application filed June 20, 2024, and the information disclosure statement (IDS) filed April 28, 2025 and August 27, 2025.
Claims 1-20 are pending. Claims 1, 11 and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 28, 2025 and August 27, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention, MEMORY CIRCUITS AND METHODS FOR OPERATING THE SAME, is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jain (US 2022/0336009).
Regarding independent claim 1 and its method claim 19, Jain discloses a memory circuit (see e.g., FIGS. 3-4), comprising:
a first memory cell (FIG. 3: 346) operatively accessible through a first access line (RDL) and a second access line (RBLB);
a first read pass-gate transistor (318) and a second read pass-gate transistor (320) coupled to the first access line and the second access line, respectively;
a first sense amplifier (322) coupled to the first access line and the second access line;
a first read enable control circuit (FIGS. 3-4: 120, especially FIG. 4: 414 and 416-424) configured to generate a first read enable signal (input node of 426) based on a clock signal (414 input, ICLKD, para. 0041: the delayed internal clock signal ICLKD); and
a second read enable control circuit (FIGS. 3-4: 120, especially FIG. 4: 426 and FIG. 3: 312) configured to generate a second read enable signal (FIG. 3: READB) by logically inverting (FIG. 4: 426) the first read enable signal, wherein the first read enable signal selectively transitions to a different logic state based on a first sense enable signal (FIG. 4: SAE);
wherein the second read enable signal (FIG. 3: READB) is configured to activate or deactivate both the first read pass-gate transistor and the second read pass-gate transistor (see FIG. 3, READB, and 318 and 320), and the first sense enable signal is configured to activate or deactivate the first sense amplifier (see FIG. 3, SAE and 322).
Further, regarding method claim 19, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Examiner has an authority to shift the burden to applicant and require applicant to either: (1) show the prior art memory device and the claimed memory device are not substantially identical; or (2) prove, by evidence, that the prior art memory device is not capable of performing the functions claimed. see MPEP 2112.01(I).
Regarding claim 2, which depends from claim 1, Jain discloses the first read enable control circuit comprises a NOR gate, and the second read enable control circuit comprises an inverter and a transistor (see FIGS. 3-4: 120).
Regarding claim 3, which depends from claim 2, Jain discloses the NOR gate has a first input configured to receive a write enable signal, a second input configured to receive a sense enable control signal that is generated according to the clock signal, and an output configured to output the first read enable signal, and wherein the first sense enable signal follows the sense enable control signal (see FIGS. 3-4, control circuitry 120 and 260).
Regarding claim 4, which depends from claim 2, which depends from claim 3, Jain discloses the inverter has an input configured to receive the first read enable signal and an output configured to provide the second read enable signal, and the transistor has a gate terminal connected to the first sense enable signal, a drain terminal connected to the first read enable signal, and a source terminal connected to ground (see FIG. 4 along with FIG. 3).
Regarding claim 5, which depends from claim 1, Jain discloses only after the first sense enable signal transitions from a first logic state to a second logic state to activate the first sense amplifier, the second read enable control circuit is configured to deactivate both the first read pass-gate transistor and the second read pass-gate transistor based on coupling the first read enable signal to ground (see FIG. 3 and accompanying disclosure).
Regarding claim 6, which depends from claim 5, Jain discloses only after the first sense enable signal transitions from the second logic state to the first logic state to deactivate the first sense amplifier, the second read enable control circuit is configured to cause both the first read pass-gate transistor and the second read pass-gate transistor to remain deactivated for a period of time based on decoupling the first read enable signal from the ground (see FIG. 3 and accompanying disclosure).
Regarding claim 20, which depends from claim 19, Jain discloses the local read enable signal is pulled up based on coupling the global read enable signal to ground, and wherein the local read enable signal is pulled down based on decoupling the global read enable signal from the ground (see FIGS. 3-4 and accompanying disclosure).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-18 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jain (US 2022/0336009).
Regarding claim 7, Jain teaches the limitations of claim 1.
Jain’s memory array (FIGS. 1-2: 110) specifically illustrates an example of a memory device that includes a first memory cell (FIG. 3: 346) claimed within the memory array.
Jain’s memory array does not explicitly disclose the claimed limitations of a second memory cell operatively accessible through a third access line and a fourth access line; a third read pass-gate transistor and a fourth read pass-gate transistor coupled to the third access line and the fourth access line, respectively; a second sense amplifier coupled to the third access line and the fourth access line; and a third read enable control circuit configured to generate a third read enable signal by logically inverting the first read enable signal that selectively transitions to a different logic state based on a second sense enable signal; wherein the third read enable signal is configured to activate or deactivate both the third read pass-gate transistor and the fourth read pass-gate transistor, and the second sense enable signal is configured to activate or deactivate the second sense amplifier.
However, expanding memory cells in a matrix-structured memory device is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply extended memory cells to a memory array, because it simply involves duplicating parts (including the control circuit and memory cells) to increase the density of memory cells in a memory array. See MPEP 2144.04(VI)(B).
Regarding claim 8, Jain teaches the limitations of claim 7.
Jain’s memory array does not explicitly disclose the second read enable control circuit is physically located next to the first memory cell along a first lateral direction and the third read enable control circuit is physically located next to the second memory cell along the first lateral direction, with the first read enable control circuit physically disposed next to the second read enable control circuit and the third read enable control circuit along a second lateral direction perpendicular to the first lateral direction.
However, physically arranging control circuitry in a balance manner is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Gupta et al. (US 12,159,664), figures 2-5f and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to placing control circuitry in a balance manner because these conventional technology are well established in the art of the memory devices.
Regarding claims 9-10, Jain teaches the limitations of claim 7.
Jain’s memory array does not explicitly disclose the first access line and the second access line belong to a first array, and the third access line and the fourth access line belong to a second array; and the second read enable control circuit and the third read enable control circuit are alternately activated.
However, alternatively activating multiple access lines in a matrix structure of a memory array is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to activating memory sub-array accordingly because these conventional technology are well established in the art of the memory devices.
This listing of claims will replace all prior versions and listings of claims in the application:
Regarding independent claim 11 and its dependent claims 12-18, Jain discloses the limitations of claims 11-18 applied to claims 1-10, with the except of the multiple of memory cells portions.
However, expanding memory cells in a matrix-structured memory device is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply extended memory cells to a memory array, because it simply involves duplicating parts (including the control circuit and memory cells) to increase the density of memory cells in a memory array. See MPEP 2144.04(VI)(B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825