DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-8, 11-14, and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2020/0243643) (hereafter Yu643).
Regarding claim 1, Yu643 discloses a semiconductor device comprising:
a substrate 102 (Fig. 25, paragraph 0014);
first (left 103A in Fig. 25, paragraph 0014) and second fin structures (right 103A in Fig. 25, paragraph 0014) extending above the substrate 102 (Fig. 25);
a metal layer 130 (Fig. 25, paragraph 0014) on the first (left 103A in Fig. 25) and second fin structures (right 103A in Fig. 25);
an isolation structure (127 and 125A in Fig. 25) extending through the metal layer 130 (Fig. 25) between the first (left 103A in Fig. 25) and second fin structures (right 103A in Fig. 25), wherein:
the isolation structure (127 and 125A in Fig. 25) is configured to electrically isolate a first portion (second 130 from the left corner of Fig. 25) of the metal layer 130 (Fig. 25) on the first fin structure (left 103A in Fig. 25) from a second portion (third 130 from the left corner of Fig. 25) of the metal layer 130 (Fig. 25) on the second fin structure (right 103A in Fig. 25), and
the isolation structure (127 and 125A in Fig. 25) has substantially vertical sidewalls; and
a passivation layer 117 (Fig. 25, paragraph 0023) between at least an upper portion of the isolation structure (127 and 125A in Fig. 25) and an adjacent portion of the metal layer 130 (Fig. 25), wherein:
the passivation layer 117 (Fig. 24) extends laterally into the metal layer 130 (Fig. 24).
Regarding claim 2, Yu643 further discloses the semiconductor device of claim 1, further comprising: a shallow trench isolation structure 107 (Fig. 24, paragraph 0015) on the substrate 102 (Fig. 24); and a recess (region of 121 formed between 107 in Fig. 24) in the shallow trench isolation structure 107 (Fig. 24) and aligned with the isolation structure (127 and 125A in Fig. 24).
Regarding claim 3, Yu643 further discloses the semiconductor device of claim 2, further comprising: a dielectric fill material 121 (Fig. 24) filling the recess (region of 121 formed between 107 in Fig. 24).
Regarding claim 5, Yu643 further discloses the semiconductor device of claim 1, wherein: the passivation layer 117 (Fig. 25, paragraph 0023, wherein “a metal oxide, such as, for example, aluminum oxide, titanium oxide, a high-k insulating material (k value of 9 or greater), such as hafnium oxide, etc”) includes at least one of a nitride, oxide, or oxynitride of the metal layer.
Regarding claim 6, Yu643 further discloses the semiconductor device of claim 1, wherein: the passivation layer 117 (Fig. 24) has a tapered structure (see Fig. 25, wherein horizontal length of upper portion of 117 between 112 is greater than horizontal length of lower portion of 117 between 102) having a thicker portion and a thinner portion, the thicker portion of the passivation layer 117 (Fig. 24) being farther from the substrate 102 (Fig. 25) than the thinner portion of the passivation layer 117 (Fig. 24).
Regarding claim 7, Yu643 further discloses the semiconductor device of claim 6, wherein: the passivation layer 117 (Fig. 24) extends laterally into the metal layer 130 (Fig. 24) by a first distance (horizontal length of upper portion of 117 between 130 in Fig. 24) at a portion of the passivation layer 117 (Fig. 24) that is farthest from the substrate 102 (Fig. 24), the passivation layer 117 (Fig. 24) extends laterally into the metal layer 130 (Fig. 24) by a second distance (horizontal length of lower portion of 117 between 107 in Fig. 24) at a portion of the passivation layer 117 (Fig. 24) that is closest to the substrate 102 (Fig. 24), and the first distance (horizontal length of upper portion of 117 between 130 in Fig. 24) is greater than the second distance (horizontal length of lower portion of 117 between 107 in Fig. 24).
Regarding claim 8, Yu643 further discloses the semiconductor device of claim 1, wherein: the passivation layer 117 (Fig. 24) has a stepped structure (see Fig. 24) having a first portion with a constant first thickness and a second portion with a constant second thickness, and the first portion (upper portion of 117 in Fig. 24) of the passivation layer 117 (Fig. 24) is thicker and farther from the substrate 102 (Fig. 24) than the second portion (lower portion of 117 in Fig. 24) of the passivation layer 117 (Fig. 24).
Regarding claim 11, Yu643 discloses a semiconductor device comprising:
a first fin structure (left 103A in Fig. 25, paragraph 0014) and a second fin structure (right 103A in Fig. 25, paragraph 0014) extending in a first direction (vertical direction in Fig. 25) on a substrate 102 (Fig. 25), the first fin structure (left 103A in Fig. 25) being spaced apart from the second fin structure (right 103A in Fig. 25) in a second direction (horizontal direction in Fig. 25), the second direction (horizontal direction in Fig. 25) crossing the first direction (vertical direction in Fig. 25);
a gate structure 130 (Fig. 25, paragraph 0014) on the first (left 103A in Fig. 25) and second fin structures (right 103A in Fig. 25);
a dielectric material (121, 127, and 125A in Fig. 25) extending through the gate structure 130 (Fig. 25) in the first direction (vertical direction in Fig. 25) and separating a first portion (second 130 from the left corner of Fig. 25) of the gate structure 130 (Fig. 25) on the first fin structure (left 103A in Fig. 25) from a second portion (third 130 from the left corner of Fig. 25) of the gate structure 130 (Fig. 25) on the second fin structure (right 103A in Fig. 25); and
a passivation layer 117 (Fig. 25, paragraph 0023) on a sidewall of the gate structure 130 (Fig. 25) adjacent the dielectric material (121, 127, and 125A in Fig. 25), the passivation layer 117 (Fig. 25) extending into the gate structure 130 (Fig. 25) in the second direction (horizontal direction in Fig. 25).
Regarding claim 12, Yu643 further discloses the semiconductor device of claim 11, wherein: the gate structure 130 (Fig. 25, paragraph 0029, wherein “titanium, tungsten, aluminum, etc”) includes a metal layer, and the passivation layer 117 (Fig. 25, paragraph 0023, wherein “a metal oxide, such as, for example, aluminum oxide, titanium oxide, a high-k insulating material (k value of 9 or greater), such as hafnium oxide, etc”) is at least one of a nitride, oxide, or oxynitride of the metal layer.
Regarding claim 13, Yu643 further discloses the semiconductor device of claim 11, wherein: the gate structure 130 (Fig. 25, paragraph 0029, wherein “titanium, tungsten, aluminum, etc”) includes at least one of Al, Ti, Si, or W, and the passivation layer 117 (Fig. 25, paragraph 0023, wherein “a metal oxide, such as, for example, aluminum oxide, titanium oxide, a high-k insulating material (k value of 9 or greater), such as hafnium oxide, etc”) includes at least one of AlOx, AlNy, AlOxNy, TiOx, TiNy, AlOxNy, SiOx, SiNy, SiOxNy, WN, WOx, or WOxNy.
Regarding claim 14, Yu643 further discloses the semiconductor device of claim 11, wherein: the passivation layer 117 (Fig. 24) has a stepped structure (see Fig. 24) having a first portion (upper portion of 117 in Fig. 24) with a constant first thickness and a second portion (lower portion of 117 in Fig. 24) with a constant second thickness, the first portion (upper portion of 117 in Fig. 24) of the passivation layer being thicker (see Fig. 24, wherein horizontal length of 117 between 132 is greater than horizontal length of 117 between 102) and farther from the substrate 102 (Fig. 24) than the second portion (lower portion of 117 in Fig. 24) of the passivation layer.
Regarding claim 16, Yu643 discloses a semiconductor device comprising:
a substrate 102 (Fig. 25, paragraph 0014);
a first fin structure (left 103A in Fig. 25, paragraph 0014) and a second fin structure (right 103A in Fig. 25, paragraph 0014) extending above the substrate 102 (Fig. 25);
a metal layer 130 (Fig. 25, paragraph 0014) on the first (left 103A in Fig. 25) and second fin structures (right 103A in Fig. 25);
an isolation structure (127 and 125A in Fig. 25) extending through the metal layer 130 (Fig. 25) and separating a first portion (second 130 from the left corner of Fig. 25) of the metal layer on the first fin structure (left 103A in Fig. 25) from a second portion (third 130 from the left corner of Fig. 25) of the metal layer on the second fin structure (right 103A in Fig. 25), the isolation structure (127 and 125A in Fig. 25) having substantially vertical sidewalls; and
at least one of a nitride, oxide, or oxynitride of the metal layer 117 (Fig. 25, paragraph 0023, wherein “a metal oxide, such as, for example, aluminum oxide, titanium oxide, a high-k insulating material (k value of 9 or greater), such as hafnium oxide, etc”) in a region of the metal layer 130 (Fig. 25) adjacent to at least an upper portion of the isolation structure (127 and 125A in Fig. 25).
Regarding claim 17, Yu643 further discloses the semiconductor device of claim 16, wherein: the at least one of a nitride, oxide, or oxynitride of the metal layer 117 (Fig. 25) becomes thinner (see Fig. 25, wherein horizontal length of upper portion of 117 between 112 is greater than horizontal length of lower portion of 117 between 102) towards the substrate 102 (Fig. 25).
Regarding claim 18, Yu643 further discloses the semiconductor device of claim 16, wherein: the at least one of a nitride, oxide, or oxynitride of the metal layer forms a passivation layer 117 (Fig. 25) having a tapered structure (see Fig. 25, wherein horizontal length of upper portion of 117 between 112 is greater than horizontal length of lower portion of 117 between 102) having a thicker portion and a thinner portion, the thicker portion being farther from the substrate 102 (Fig. 25) than the thinner portion.
Regarding claim 19, Yu643 further discloses the semiconductor device of claim 17, wherein: the at least one of a nitride, oxide, or oxynitride of the metal layer 117 (Fig. 24) forms a passivation layer 117 (Fig. 24) having a stepped structure (see Fig. 24) having a first portion (upper portion of 117 in Fig. 24) with a constant first thickness and a second portion (lower portion of 117 in Fig. 24) with a constant second thickness, the first portion (upper portion of 117 in Fig. 24) of the passivation layer being thicker (see Fig. 24, wherein horizontal length of 117 between 132 is greater than horizontal length of 117 between 102) and farther from the substrate 102 (Fig. 24) than the second portion (lower portion of 117 in Fig. 24) of the passivation layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yu643 as applied to claim 2 above, and further in view of Chen et al. (US 2019/0165137) (hereafter Chen), in further view of Yu et al. (US 2017/0125411) (hereafter Yu411).
Regarding claim 4, Yu643 discloses the semiconductor device of claim 2, however Yu643 does not disclose the isolation structure has a taper of no more than 2˚.
Chen discloses the isolation structure 50 (Fig. 9A, paragraph 0039, wherein “positive taper profile (e.g., sidewalls of components abutting the gate cut-fill structures 50 have angles with the bottom surfaces of the components adjoining the sidewalls is less than 90 degrees interior to those components, respectively)”) has a taper of no more than 2˚
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Yu643 to form the isolation structure having a taper of no more than 2˚, as taught by Chen, since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing taper profile from the structures listed in Yu643 (e.g. taper profile, vertical profile, or re-entrant profile); if this leads to the anticipated success, in the instant case providing an isolation structure separating the adjacent gates, it is likely the product not of innovation but of ordinary skill. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Yu643 and Chen do not disclose the recess has a depth of no more than 15 nm.
Yu411 discloses the recess 130 (Fig. 6A, paragraph 0031) has a depth (see paragraph 0032, wherein “range from about 1 nm to about 10 nm”) of no more than 15 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Yu643 in view of Chen to include the recess having a depth of no more than 15 nm, as taught by Yu411, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 9, 10, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu643 as applied to claims 8, 1, 11 and 17 above, and further in view of Chang et al. (US 2020/0105581) (hereafter Chang).
Regarding claim 9, Yu643 further discloses the semiconductor device of claim 8, further comprising: a shallow trench isolation structure 107 (Fig. 24, paragraph 0015) on the substrate 102 (Fig. 24).
Yu643 does not disclose the isolation structure extends below an uppermost surface of the shallow trench isolation structure, and the second portion of the passivation layer is entirely above the uppermost surface of the shallow trench isolation structure.
Chang discloses the isolation structure 292 (Fig. 24B, paragraph 0055) extends below an uppermost surface of the shallow trench isolation structure 160 (Fig. 24B, paragraph 0055), and the second portion of the passivation layer 290 (Fig. 24B, paragraph 0048, wherein “SiOx, SiON, Si.sub.3N.sub.4, SiOCN, SiC, SiGe, metals, or combinations thereof”) is entirely above the uppermost surface of the shallow trench isolation structure 160 (Fig. 24B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Yu643 to form the isolation structure extends below an uppermost surface of the shallow trench isolation structure, and the second portion of the passivation layer is entirely above the uppermost surface of the shallow trench isolation structure, as taught by Chang, since the isolation structure 292 (Fig. 24B, paragraph 0056) and the at least one of a nitride, oxide, or oxynitride of the metal layer 290 (Fig. 24B, paragraph 0066) provide electrical isolation between gates 284 (Chang, Fig. 24B, paragraph 0056).
Regarding claim 10, Yu643 further discloses the semiconductor device of claim 1, further comprising: a shallow trench isolation structure 107 (Fig. 24, paragraph 0015) on the substrate 102 (Fig. 24).
Yu643 does not disclose the isolation structure extends below an uppermost surface of the shallow trench isolation structure, and the passivation layer is entirely above the uppermost surface of the shallow trench isolation structure.
Chang discloses the isolation structure 292 (Fig. 24B, paragraph 0055) extends below an uppermost surface of the shallow trench isolation structure 160 (Fig. 24B, paragraph 0055), and the passivation layer 290 (Fig. 24B, paragraph 0048, wherein “SiOx, SiON, Si.sub.3N.sub.4, SiOCN, SiC, SiGe, metals, or combinations thereof”) is entirely above the uppermost surface of the shallow trench isolation structure 160 (Fig. 24B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Yu643 to form the isolation structure extends below an uppermost surface of the shallow trench isolation structure, and the passivation layer is entirely above the uppermost surface of the shallow trench isolation structure, as taught by Chang, since the isolation structure 292 (Fig. 24B, paragraph 0056) and the at least one of a nitride, oxide, or oxynitride of the metal layer 290 (Fig. 24B, paragraph 0066) provide electrical isolation between gates 284 (Chang, Fig. 24B, paragraph 0056).
Regarding claim 15, Yu643 further discloses the semiconductor device of claim 11, further comprising: a shallow trench isolation structure 107 (Fig. 24, paragraph 0015) on the substrate 102 (Fig. 24)
Yu643 does not disclose the dielectric material extends below an uppermost surface of the shallow trench isolation structure, and the passivation layer is entirely above the uppermost surface of the shallow trench isolation structure.
Chang discloses the dielectric material 292 (Fig. 24B, paragraph 0055) extends below an uppermost surface of the shallow trench isolation structure 160 (Fig. 24B, paragraph 0055), and the passivation layer 290 (Fig. 24B, paragraph 0048, wherein “SiOx, SiON, Si.sub.3N.sub.4, SiOCN, SiC, SiGe, metals, or combinations thereof”) is entirely above the uppermost surface of the shallow trench isolation structure 160 (Fig. 24B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Yu643 to form the dielectric material extends below an uppermost surface of the shallow trench isolation structure, and the passivation layer is entirely above the uppermost surface of the shallow trench isolation structure, as taught by Chang, since the isolation structure 292 (Fig. 24B, paragraph 0056) and the at least one of a nitride, oxide, or oxynitride of the metal layer 290 (Fig. 24B, paragraph 0066) provide electrical isolation between gates 284 (Chang, Fig. 24B, paragraph 0056).
Regarding claim 20, Yu643 further discloses the semiconductor device of claim 17, further comprising: a shallow trench isolation structure 107 (Fig. 24, paragraph 0015) on the substrate 102 (Fig. 24).
Yu643 does not disclose the isolation structure extends below an uppermost surface of the shallow trench isolation structure, and the at least one of a nitride, oxide, or oxynitride of the metal layer is entirely above the uppermost surface of the shallow trench isolation structure.
Chang discloses the isolation structure 292 (Fig. 24B, paragraph 0055) extends below an uppermost surface of the shallow trench isolation structure 160 (Fig. 24B, paragraph 0055), and the at least one of a nitride, oxide, or oxynitride of the metal layer 290 (Fig. 24B, paragraph 0048, wherein “SiOx, SiON, Si.sub.3N.sub.4, SiOCN, SiC, SiGe, metals, or combinations thereof”) is entirely above the uppermost surface of the shallow trench isolation structure 160 (Fig. 24B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Yu643 to form the isolation structure extends below an uppermost surface of the shallow trench isolation structure, and the at least one of a nitride, oxide, or oxynitride of the metal layer is entirely above the uppermost surface of the shallow trench isolation structure, as taught by Chang, since the isolation structure 292 (Fig. 24B, paragraph 0056) and the at least one of a nitride, oxide, or oxynitride of the metal layer 290 (Fig. 24B, paragraph 0066) provide electrical isolation between gates 284 (Chang, Fig. 24B, paragraph 0056).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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