Prosecution Insights
Last updated: April 19, 2026
Application No. 18/749,166

CROSSBAR CIRCUITS FOR PERFORMING CONVOLUTION OPERATIONS

Non-Final OA §102§103
Filed
Jun 20, 2024
Examiner
BERMUDEZ LOZADA, ALFREDO
Art Unit
2825
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tetramem Inc.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
91%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
461 granted / 518 resolved
+21.0% vs TC avg
Minimal +2% lift
Without
With
+1.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
39 currently pending
Career history
557
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
40.7%
+0.7% vs TC avg
§102
44.3%
+4.3% vs TC avg
§112
8.4%
-31.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 518 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is responsive to the following communications: the Application filed June 20, 2024. Claims 13-25 are pending. Claims 1-12 are canceled by Preliminary Amendments. Claim 13 is independent. Information Disclosure Statement Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on October 7, 2024, February 21, 2025, April 3, 2025 and August 28, 2025. These IDSs have been considered. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 13 and 17-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Merced Grafals et al. (U.S. 9,691,479; hereinafter “Merced Grafals”). PNG media_image1.png 801 1266 media_image1.png Greyscale PNG media_image2.png 956 966 media_image2.png Greyscale Regarding independent claim 13, Merced Grafals discloses a first crossbar circuit (see Examiner’s Markup Merced Grafals Figure 2) comprising a first plurality of cross-point devices (Fig. 2: 203) connecting a plurality of word lines (Fig. 2: 201), a first plurality of select lines (Fig. 2: 220s), and a first plurality of bit lines (Fig. 2: 202), wherein each of the first plurality of select lines (Fig. 2: 220s) is connected to multiple cross-point devices (Fig. 2: 203) of the first crossbar circuit (see Examiner’s Markup Merced Grafals Figure 2) that are connected to the plurality of word lines (Fig. 2: 201) and one of the first plurality of bit lines (Fig. 2: 202); and a second crossbar circuit (see Examiner’s Markup Merced Grafals Figure 2) comprising a second plurality of cross-point devices (Fig. 2: 203) connecting to the plurality of word lines (Fig. 2: 201), a second plurality of select lines (Fig. 2: 220s), and a second plurality of bit lines (Fig. 2: 202), wherein the second plurality of select lines (Fig. 2: 220s) comprises a first select line (see Examiner’s Markup Merced Grafals Figure 2) connecting a first group of the second plurality of cross-point devices (see Examiner’s Markup Merced Grafals Figure 2) and a second select line (see Examiner’s Markup Merced Grafals Figure 2) connecting a second group of the second plurality of cross-point devices (see Examiner’s Markup Merced Grafals Figure 2), and wherein the first group of the second plurality of cross-point devices comprises a first cross-point device connecting a first word line (see Examiner’s Markup Merced Grafals Figure 2) and a first bit line (see Examiner’s Markup Merced Grafals Figure 2) and a second cross-point device connecting a second word line and a second bit line (see Examiner’s Markup Merced Grafals Figure 2), and wherein the second group of the second plurality of cross-point devices comprises a third cross- point device connecting a third word line and the first bit line (see Examiner’s Markup Merced Grafals Figure 2) and a fourth cross-point device connecting a fourth word line and the second bit line (see Examiner’s Markup Merced Grafals Figure 2). Regarding claim 17, Merced Grafals discloses a first selection logic (see Second Examiner’s Markup Merced Grafals Figure 2) connected to the first plurality of cross-point devices (Fig. 2: 203) through the first plurality of select lines (Fig. 2: 220s), wherein the first selection logic is configured to selectively enable one or more of the first plurality of cross-point devices via the first plurality of select lines (see col. 9, ll. 42-50); and a second selection logic (see Second Examiner’s Markup Merced Grafals Figure 2) connected to the second plurality of cross-point devices (Fig. 2: 203) through the second plurality of select lines (Fig. 2: 220s), wherein the second selection logic is configured to selectively enable one or more of the first plurality of cross-point devices via the second plurality of select lines (see col. 10, ll. 53-67; col. 11, ll. 1-3 and col. 11, ll. 31-39). Regarding claim 18, Merced Grafals discloses wherein the second selection logic comprises a plurality of selection registers (Fig. 2: 211), wherein the first group of the second plurality of cross-point devices (see Examiner’s Markup Merced Grafals Figure 2) is connected to a first selection register (Fig. 2: 211-6/211-5) via the first select line (see Examiner’s Markup Merced Grafals Figure 2). Regarding claim 19, Merced Grafals discloses wherein a second selection register (Fig. 2: 211-2/211-1) of the second selection logic is connected to the second group of the second plurality of cross-point devices (see Examiner’s Markup Merced Grafals Figure 2) via the second select line (see Examiner’s Markup Merced Grafals Figure 2). Regarding claim 20, Merced Grafals discloses wherein the first group of the second plurality of cross-point devices are enabled while a first supply voltage is applied to the first select line of the second plurality of select lines (Fig. 2: voltage applied to 211-6). Regarding claim 21, Merced Grafals discloses wherein a group of the first plurality of cross-point devices (see Examiner’s Markup Merced Grafals Figure 2) are enabled while a second voltage (Fig. 2: a voltage applied to 205-3) is applied to a third select line of the first plurality of select lines (see Examiner’s Markup Merced Grafals Figure 2), wherein the group of the first plurality of cross-point devices are connected to the third select line (see Examiner’s Markup Merced Grafals Figure 2) and the plurality of word lines (Fig. 2: 201). Regarding claim 22, Merced Grafals discloses a programming logic configured to programming the selectively enabled first plurality of cross-point devices and the selectively enabled second plurality of cross-point devices (Fig. 1: 101 and 111-113). Regarding claim 23, Merced Grafals discloses wherein the second plurality of select lines are not parallel to the second plurality of bit lines (Fig. 2: lines 220s are not parallel to bit lines 202). Regarding claim 24, Merced Grafals discloses wherein the second plurality of select lines are not parallel to the plurality of word lines (Fig. 2: lines 220s are not parallel to word lines 201). Regarding claim 25, Merced Grafals discloses wherein at least one of the second plurality of cross-point devices comprises a transistor and a memristor (see Fig. 3 and Fig. 9. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Merced Grafals et al. (U.S. 9,691,479; hereinafter “Merced Grafals”) in view of Hu et al. (U.S. 2018/0350433; hereinafter “Hu”). Regarding claim 14, Merced Grafals discloses the limitations with respect to claim 13. Furthermore, Merced Grafals teaches wherein the first plurality of cross-point devices and the second plurality of cross-point devices are connected to a word line logic through the plurality of word lines (Fig. 2: 211s). However, Merced Grafals is silent with respect to the word line logic comprises a plurality of digital-to-analog converters. Similar to Merced Grafals, Hu teaches an apparatus comprising first and second crossbar circuit (Fig. 2: 220s) comprising a plurality of cross-point devices (Fig. 2: 230) connecting a plurality of word lines (Fig. 2: 210). Furthermore, Hu teaches the plurality of cross-point devices are connected to a word line logic through the plurality of word lines, wherein the word line logic comprises a plurality of digital-to-analog converters (see pages 3-4, par. 0037). Since Hu and Merced Grafals are from the same field of endeavor, the teachings described by Hu would have been recognized in the pertinent art of Merced Grafals. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Hu with the teachings of Merced Grafals for the purpose of minimize sneak path currents in the array, see Hu’s page 4, par. 0041. Regarding claim 15, Merced Grafals discloses the limitations with respect to claim 13. Furthermore, Merced Grafals teaches wherein the first plurality of cross-point devices is connected to a sensing circuit through the first plurality of bit lines (Fig. 2: 210s). However, Merced Grafals is silent with respect to the sensing circuit comprises a plurality of analog-to-digital converters. Similar to Merced Grafals, Hu teaches an apparatus comprising first and second crossbar circuit (Fig. 2: 220As) comprising a plurality of cross-point devices (Fig. 2: 230) connected to a sensing circuit (Fig. 4: 418) through a plurality of bit lines (Fig. 2: 220). Furthermore, Hu teaches the plurality of cross-point devices are connected to a sensing circuit through the plurality of bit lines, wherein the sensing circuit comprises a plurality of analog-to-digital converters (see pages 3-4, par. 0037). Since Hu and Merced Grafals are from the same field of endeavor, the teachings described by Hu would have been recognized in the pertinent art of Merced Grafals. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Hu with the teachings of Merced Grafals for the purpose of minimize sneak path currents in the array, see Hu’s page 4, par. 0041. Regarding claim 16, Merced Grafals in combination with Hu teaches the limitation with respect to claim 15. Furthermore, Merced Grafals teaches the second plurality of cross-point devices are connected to the sensing circuit (Fig. 2: 210s) through the second plurality of bit lines (Fig. 2: 202). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
Read full office action

Prosecution Timeline

Jun 20, 2024
Application Filed
Nov 07, 2025
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
91%
With Interview (+1.6%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 518 resolved cases by this examiner. Grant probability derived from career allow rate.

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