DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/20/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6, 8, 10-15 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (PG Pub 2017/0365581; hereinafter Yu).
PNG
media_image1.png
416
706
media_image1.png
Greyscale
Regarding claim 1, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches a package structure 300, comprising:
a first semiconductor die 104a having a plurality of first conductive posts (annotated “post-1”);
a second semiconductor die 105a having a plurality of second conductive posts (annotated “post-2”), wherein a height of the second semiconductor die (annotated “h-2”) is smaller than a height of the first semiconductor die (annotated “h-1”) (see Fig. 5n);
a plurality of connecting pillars (annotated “pillars”) joined (thru annotated “bump”) with the plurality of second conductive posts of the second semiconductor die, wherein a top surface of the plurality of connecting pillars is coplanar with a top surface of the plurality of first conductive posts (see Fig. 5n);
an insulating encapsulant 109, encapsulating the first semiconductor die, the second semiconductor die, and the plurality of connecting pillars (see Fig. 5n); and
a redistribution layer 102 disposed on the insulating encapsulant and electrically connected (via 102b) to the plurality of first conductive posts and the plurality of connecting pillars (see Fig. 5n).
Regarding claim 2, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches an underfill structure 108 covering and contacting the plurality of second conductive posts (“post-2”) of the second semiconductor die 105a and the plurality of connecting pillars(“pillars”) (see Fig. 5n).
Regarding claim 6, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches a plurality of conductive bumps (annotated “bumps”) physically joining the plurality of second conductive posts (“post-2”) of the second semiconductor die 105a to the plurality of connecting pillars (“pillars”) (see Fig. 5n).
Regarding claim 8, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches a structure 300, comprising:
a first semiconductor die 104a and a second semiconductor die 105a, wherein the first semiconductor die and the second semiconductor die has a first height difference (annotated “h1” and “h2” respectively);
a plurality of conductive bumps (annotated “bumps”) disposed on and connected to the second semiconductor die (see Fig. 5n);
a plurality of connecting pillars (annotated “pillars”) disposed on and connected to the plurality of conductive bumps (see Fig. 5n), wherein a sum of a height of one of the plurality of conductive bumps and a height of one of the plurality of connecting pillars is equal to the first height difference (see Fig. 5n); and
an underfill structure 108 disposed in between the first semiconductor die and the second semiconductor die and covering and contacting the plurality of conductive bumps and the plurality of connecting pillars (see Fig. 5n).
Regarding claim 10, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches first semiconductor die 104a comprises a first substrate (not shown; para [0029]), and the second semiconductor die 105a comprises a second substrate (not shown; para [0029). Yu does not teach the first substrate has a greater thickness than the second substrate.
However, one of ordinary skill in the art would have found it obvious to alter the size of the semiconductor chip to be equal to, less than or greater than one another since the court has held changes in size normally require only ordinary skill in the art and hence are considered routine expedients are discussed below (MPEP § 2144).
Furthermore, according to MPEP § 2144.05(IV)(A) “[W]here the facts in a prior legal decision are sufficiently similar to those in an application under examination, the examiner may use the rationale used by the court. Examples directed to various common practices which the court has held normally require only ordinary skill in the art and hence are considered routine expedients are discussed below.” see
In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation), see Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree “will not sustain a patent”); and see In re Williams, 36 F.2d 436, 438 (CCPA 1929) (“It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”).
Regarding claim 11, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches a maximum height of the underfill structure (annotated “p-2” in Fig. 5n) is less than a height of the first semiconductor die (see Fig. 5n); and a height of the first semiconductor die (top of 104a). Yu does not teach the maximum height of the underfill structure is equal to a height of the first semiconductor die.
However, one of ordinary skill in the art would have found it obvious to alter the size of the underfill structure to be equal to, less than or greater than the height of the first semiconductor die; since the court has held changes in size normally require only ordinary skill in the art and hence are considered routine expedients are discussed below (MPEP § 2144).
Furthermore, according to MPEP § 2144.05(IV)(A) “[W]here the facts in a prior legal decision are sufficiently similar to those in an application under examination, the examiner may use the rationale used by the court. Examples directed to various common practices which the court has held normally require only ordinary skill in the art and hence are considered routine expedients are discussed below.” see
In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation), see Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree “will not sustain a patent”); and see In re Williams, 36 F.2d 436, 438 (CCPA 1929) (“It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”).
Regarding claim 12, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches at least one sidewall (e.g. top sidewall) of the first semiconductor die 104a and at least one sidewall (e.g. top sidewall) of the second semiconductor die 105a are free and exposed from the underfill structure 108 (see Fig. 5n).
Regarding claim 13, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches an insulating encapsulant 109 encapsulating the first semiconductor die 104a, the second semiconductor die 105a and the underfill structure 109 (see Fig. 5n).
Regarding claim 14, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches a redistribution layer 102 disposed on and electrically connected to the first semiconductor die 104a and the plurality of connecting pillars (“pillars”) (see Fig. 5n).
Regarding claim 15, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches a structure 300, comprising:
a first semiconductor die 104a having a plurality of first conductive posts (“post-1”);
a second semiconductor die 105a having a plurality of second conductive posts (“post-2”);
an underfill structure 108 having a first portion (annotated “p1”) and a second portion (annotated “p2”), wherein the first portion of the underfill structure is disposed on the second semiconductor die and directly covering the plurality of second conductive posts (see Fig. 5n), and wherein the second portion of the underfill structure is located in between the first semiconductor die and the second semiconductor die and has a greater height than the first portion (see Fig. 5n); and
an insulating encapsulant 109 surrounding the first semiconductor die, the second semiconductor die and the underfill structure (see Fig. 5n).
Regarding claim 17, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches a height of the second portion of the underfill structure (annotated “p-2” in Fig. 5n) is less than a height of the first semiconductor die (see Fig. 5n); and a height of the first semiconductor die (top of 104a). Yu does not teach the height of the second portion of the underfill structure is equal to a height of the first semiconductor die.
However, one of ordinary skill in the art would have found it obvious to alter the size of the underfill structure to be equal to, less than or greater than the height of the first semiconductor die; since the court has held changes in size normally require only ordinary skill in the art and hence are considered routine expedients are discussed below (MPEP § 2144).
Furthermore, according to MPEP § 2144.05(IV)(A) “[W]here the facts in a prior legal decision are sufficiently similar to those in an application under examination, the examiner may use the rationale used by the court. Examples directed to various common practices which the court has held normally require only ordinary skill in the art and hence are considered routine expedients are discussed below.” see
In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation), see Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree “will not sustain a patent”); and see In re Williams, 36 F.2d 436, 438 (CCPA 1929) (“It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”).
Regarding claim 18, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches a plurality of conductive bumps (“bump”) disposed on the plurality of second conductive posts (“post-2”); and a plurality of connecting pillars (“pillars”) disposed on the plurality of conductive bumps (see Fig. 5n), wherein the plurality of conductive bumps and the plurality of connecting pillars are embedded in the underfill structure (see Fig. 5n).
Regarding claim 19, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches the plurality of second conductive posts (“post-2”) and the plurality of connecting pillars (“pillars”) have linear sidewalls (vertical), and the plurality of conductive bumps (“bump”) has curved sidewalls (see Fig. 5n).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
2. Claim(s) 5, 7, 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, applied to claim 1 (or claim 15) above, and further in view of Hsu et al. (PG Pub 2018/0033770; hereinafter Hsu).
Regarding claim 5, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches the plurality of first conductive posts (“post-1”) of the first semiconductor die 104a. Yu does not teach a protection layer covering the plurality of first conductive posts.
PNG
media_image2.png
536
922
media_image2.png
Greyscale
In the same field of endeavor, refer to Fig. 2k-provided above, Hsu teaches a semiconductor package structure 1 comprising: a protection layer 26 covering a plurality of first conductive posts 34p of a first semiconductor die 34 (see Fig. 2k).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the protection layer over the plurality of first conductive posts, as taught by Hsu, to provide protection to the first conductive posts from subsequent manufacturing process post deposition.
Regarding claim 7, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches the insulating encapsulant 109 surrounding the first semiconductor die 104a and the second semiconductor die 105a (see Fig. 5n), Yu does not explicitly teach “a plurality of through insulator vias embedded in the insulating encapsulant and surrounding the first semiconductor die and the second semiconductor die.”
In the same field of endeavor, refer to Fig. 2k-provided above, Hsu teaches a semiconductor package structure 1 comprising: a plurality of through insulator vias 20 embedded in an insulating encapsulant 30 and surrounding a first semiconductor die 34 and a second semiconductor die 32 (see Fig. 2k).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a plurality of through insulator vias embedded in the insulating encapsulant and surrounding the first semiconductor die and the second semiconductor die, as taught by Hsu, to provide electrical communication between the redistribution layer and additional packages.
Regarding claim 9, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches the first semiconductor die 104a comprises a plurality of first conductive posts (“post-1”) and the underfill structure 108 (see Fig. 5n). Yu does not teach the underfill structure is physically separated from the plurality of first conductive posts.
In the same field of endeavor, refer to Fig. 2k-provided above, Hsu teaches a semiconductor package structure 1 comprising: a first semiconductor die 34 comprises a plurality of first conductive posts 34p within a protection layer 26.
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the protection layer over the plurality of first conductive posts, as taught by Hsu, to provide the protection layer to the first conductive posts to aid in protecting the conductive posts from subsequent manufacturing process post deposition.
Note: by incorporating the protection layer over the first conductive posts the claimed limitation of “the underfill structure is physically separated from the plurality of first conductive posts” would be taught.
Regarding claim 16, refer to the Examiner’s mark-up of Fig. 5n provided above, Yu teaches the second portion (“p-2”) of the underfill structure 108 is contacting sidewalls of the first semiconductor die 104a (see Fig. 5n). Yu does not teach the underfill structure is physically separated from the plurality of first conductive posts of the first semiconductor die.
In the same field of endeavor, refer to Fig. 2k-provided above, Hsu teaches a semiconductor package structure 1 comprising: a first semiconductor die 34 comprises a plurality of first conductive posts 34p with a protection layer 26.
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the protection layer over the plurality of first conductive posts, as taught by Hsu, to provide a protection layer to the first conductive posts to aid in protecting the conductive posts from subsequent manufacturing process post deposition.
Note: by incorporating the protection layer over the first conductive posts the claimed limitation of “underfill structure is physically separated from the plurality of first conductive posts of the first semiconductor die” would be taught.
Allowable Subject Matter
3. Claims 3-4 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 3, a top surface of the underfill structure is coplanar with the top surface of the plurality of connecting pillars and the top surface of the plurality of first conductive posts.
Claim 4 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 4, the underfill structure is physically separated from the plurality of first conductive posts of the first semiconductor die.
Claim 20 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 20, a top surface and a bottom surface of the first semiconductor die are aligned with a top surface and a bottom surface of the second portion of the underfill structure.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/ALI NARAGHI/ Primary Examiner, Art Unit 2817
Prosecution Insights