Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
I. Clarity and Boundary Ambiguities
1. "in parallel with": The phrase "the first plurality of vertical interconnection portions is in parallel with the embedded sub-package" is indefinite because it is unclear whether "in parallel" connotes geometric alignment/orientation or electrical circuit topology.
2. "forming a sub-package substrate on...": Reciting forming the sub-package substrate "on" the second plurality of dice, vertical interconnection portions, and horizontal interconnection portion simultaneously renders the physical spatial relationship unclear, as these components reside on differing planes.
3. "attaching solder bumps...": The step of "attaching solder bumps, such that the solder bumps are electrically coupled..." fails to specify the physical structure or surface to which the solder bumps are attached.
II. Internal Structural and Procedural Contradictions
1. Spatial Contradiction in Substrate Attachment: The claim requires attaching the horizontal interconnection portion "on" the second plurality of dice, and then forming a sub-package substrate "on" the dice, vertical interconnection portions, and horizontal interconnection portion. Forming the sub-package substrate on all three elements creates a spatial impossibility, as the horizontal interconnect obscures the surface of the dice.
2. Interconnection Routing Contradiction: The claim recites disposing the first plurality of dice "on the front side of the package substrate" while the embedded sub-package is attached to "the back side of the package substrate", yet claims the first plurality of dice are connected to each other "through the embedded sub-package". The first plurality of dice cannot connect directly through the embedded sub-package without intervening routing through the package substrate.
3. Temporal / Process Sequence Contradiction: The claim requires "molding the embedded sub-package and the first plurality of vertical interconnection portions" prior to placing the first plurality of dice, creating a process impossibility where the vertical interconnection portions are molded to couple to the first plurality of dice before those dice are introduced to the assembly.
Regarding Dependent Claims 9–14:
Claims 9–14 are also rejected under 35 U.S.C. 112(b) as dependent on an indefinite independent claim. Furthermore, dependent claims 9–14 inherit and exacerbate the indefiniteness of Claim 8 due to critical ambiguities regarding process timing, manufacturing sequence, and physical spatial relationships:
Unclear Manufacturing Sequence & Temporal Order: The dependent claims recite additional forming, molding, and singulation steps (e.g., forming vias/pillars and singulating them in claims 9–10, or embedding thermal vias across multiple substrates in claim 12) without establishing a clear relative timeline or process order with respect to the steps of Claim 8. It is unclear when these structures are formed relative to the surrounding molding and substrate creation steps, creating confusion as to whether components are being manipulated before, during, or after package assembly.
Spatial Conflicts of Element Boundaries and Placement: As a result of this ambiguous process sequence, the dependent claims present unresolved spatial conflicts regarding where the physical elements actually reside in the final package structure. For example, claim 12 recites thermal conductive vias embedded in both the sub-package substrate and the package substrate simultaneously, while claim 13 recites a base thermal interface material layer beneath the embedded sub-package in direct thermal contact with the second plurality of semiconductor dice. Because these dice and substrates are encapsulated and built at different stages of the method, these steps create direct spatial contradictions regarding physical contact, accessibility, and structural placement within the package assembly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220359358 A1)
CLAIM 8. Kim teaches a method for forming a semiconductor package, comprising:
providing a first plurality of semiconductor dice 360, 370, 380, and a second plurality of semiconductor dice 310, 320, 350 (Fig. 12);
forming an embedded sub-package (Fig. 12), comprising:
forming a second plurality of vertical interconnection portions 410 on and electrically coupled to the second plurality of semiconductor dice 310, 320, 350;
attaching at least one horizontal interconnection portion 340 on the second plurality of semiconductor dice 310, 320, 350, wherein at least two of the second plurality of semiconductor dice 310, 320, 350 are electrically connected to each other via the at least one horizontal interconnection portion 340;
molding 500/460/420 the second plurality of semiconductor dice 310, 320, 350, the second plurality of vertical interconnection portions 410 and the at least one horizontal interconnection portion 340;
forming a sub-package substrate 250 on the second plurality of semiconductor dice 310, 320, 350, the second plurality of vertical interconnection portions and the at least one horizontal interconnection portion, wherein the second plurality of vertical interconnection portions is electrically coupled to the sub-package substrate, wherein each of the second plurality of semiconductor dice 310, 320, 350 is electrically coupled to the sub-package substrate through at least one of the second plurality of vertical interconnection portions (Fig. 12);
forming a first plurality of vertical interconnection portions 410;
molding the embedded sub-package and the first plurality of vertical interconnection portions, wherein the first plurality of vertical interconnection portions 410 is in parallel with the embedded sub-package (Fig. 12);
attaching solder bumps 335/170, such that the solder bumps are electrically coupled to the first plurality of vertical interconnection portions; forming a package substrate on the embedded sub-package and the first plurality of vertical interconnection portions, wherein the package substrate comprises a front side and a back side, wherein the first plurality of vertical interconnection portions and the sub-package substrate of the embedded sub-package are attached to and electrically coupled to the back side of the package substrate (Fig. 12); and
disposing the first plurality of semiconductor dice 360, 370, 380 on the front side of the package substrate, wherein the first plurality of semiconductor dice 360, 370, 380 is electrically coupled to the package substrate, wherein the first plurality of semiconductor dice 360, 370, 380 is electrically coupled to each other through the embedded sub-package, wherein each of the first plurality of semiconductor dice 360, 370, 380 is electrically coupled to one of the first plurality of vertical interconnection portions (Fig. 12).
Regarding the process sequence and spatial arrangement of the package components, it would have ben obvious to one of ordinary skill in the art at the time of the invention to modify or adjust the order of processing the steps and the relative position of the elements. Claim 8 recites a series of method steps without establishing a strict temporal sequence or an unambiguous spatial layout among the sub-package substrate, horizontal interconnect, and parallel vertical interconnection portions. In semiconductor package manufacturing, the specific order of executing build-up redistribution layer (RDL) formation, molding operations, and interconnect attachments constitutes a matter of routine design choice and process optimization. One of ordinary skill in the art would have recognized that the order of forming, molding, and attaching these components can be varied or performed concurrently according to standard packaging workflows to achieve predictable structural and electrical results.
CLAIM 9. Kim teaches the method of claim 8, wherein forming a first plurality of vertical interconnection portions comprises: molding multiple conductive pillars; forming a redistribution layer on the multiple conductive pillars, wherein the multiple conductive pillars are electrically connected to the redistribution layer; performing singulation to the multiple conductive pillars to obtain a first plurality of vertical interconnection portions (Fig. 12 & ¶35- the via structure is single structure and is a connection via substrate that is disposed on the substrate. Being a single via connection substrate, it is obvious if not inferred undergo some form of singulation processing step.).
CLAIM 10. Kim teaches the method of claim 8, wherein forming a first plurality of vertical interconnection portions comprises: forming multiple vias in a dielectric layer; filling a conductive material in the multiple vias to form multiple conductive vias; forming a redistribution layer on the multiple conductive vias, wherein the multiple conductive vias are electrically connected to the redistribution layer; performing singulation to the multiple conductive vias to obtain a first plurality of vertical interconnection portions (Fig. 12 & ¶35- the via structure is single structure and is a connection via substrate that is disposed on the substrate. Being a single via connection substrate, it is obvious if not inferred undergo some form of singulation processing step.).
CLAIM 11. Kim teaches the method of claim 8, further comprising: forming an interconnection portion heat spreader 700 in thermal contact with the at least one horizontal interconnection portion (Fig. 12).
CLAIM 12. Kim teaches the method of claim 11, wherein forming an interconnection portion heat spreader comprises forming thermal conductive vias embedded in the sub-package substrate and the package substrate (Fig. 12).
CLAIM 13. Kim teaches the method of claim 8, further comprising: providing a base board; forming a base thermal interface material layer beneath the embedded sub-package; mounting the solder bumps on the base board, wherein the base thermal interface material layer is in thermal contact with the second plurality of semiconductor dice (Fig. 12).
CLAIM 14. Kim teaches the method of claim 13, further comprising: forming a top thermal interface material layer on the first plurality of semiconductor dice; disposing a top heat spreader on the top thermal interface material layer (Fig. 12).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
9/21/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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