DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on June 21, 2024 has been fully considered by the examiner.
Specification
3. The disclosure is objected to because of the following informalities.
In ¶ [0009], lines 7-8 should read “IC memory chip [[102]] 104.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1, 3-4, 7, 9-10, and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lo, et al (US 9640242 B1), hereinafter Lo.
Regarding independent claim 1, Lo teaches an integrated circuit (IC) memory device (FIG. 2, 112, part of SoC IC 102) comprising:
an array of storage cells configured into multiple regions (FIG. 2, Data Banks 0..3 of DRAM memory 115);
monitoring circuitry coupled to each of the multiple regions (FIG. 2, Monitor Module 114, Temp Sensors 157A; Col. 2, ll. 21-24 teach “the monitored temperature(s) may be read from temperature sensors located within the memory subsystem and uniquely associated with the various banks that make up the memory component), the monitoring circuitry to detect and generate per-region operating parameter information (Col. 2, ll. 30-32 teach “based on the temperature, determine temperature scaling factors for each of the banks in the multi-bank memory component”); and
refresh circuitry (FIG. 2, temperature compensated memory refresh (TCMR) module 202) to generate per-region refresh information for the multiple regions based on the per-region operating parameter information (see FIG. 3 example thermal cases and associated refresh scaling factors; Col. 8, l. 48 – Col. 9, l. 52).
Regarding claim 3, Lo teaches the limitations of claim 1.
Lo further teaches the array of storage cells comprises:
dynamic random access memory (DRAM) storage cells (FIG. 2, 115; Col. 2, ll. 6-9).
Regarding claim 4, Lo teaches the limitations of claim 1.
Lo further teaches storage to store the per-region refresh information (Col. 7, ll. 56-60 teach “one or more of the method steps described herein may be implemented by executable instructions and parameters stored in the memory subsystem 112 or as from the monitor module 114 and/or the TCMR module 202”).
Regarding claim 7, Lo teaches the limitations of claim 1.
Lo further teaches the monitoring circuitry comprises:
at least one of
temperature sensing circuitry (FIG. 2, 157A);
voltage sensing circuitry; or
access count circuitry.
Regarding claim 9, Lo teaches the limitations of claim 1.
Lo further teaches the refresh circuitry generates the per-region refresh information as representations of relative refresh rates for the multiple regions (FIG. 3 and Col. 1, ll. 26-61 teach a scaling factor that acts as a multiplier for a baseline refresh cycle time, and so each scaling factor represents a value relative to the baseline).
Regarding independent claim 10, Lo teaches a method of operation in a memory device (e.g., FIG. 6), the method comprising:
storing data in an array of storage cells (Col. 14, ll. 9-13; FIG. 6, “refresh” implies data is stored), the array of storage cells configured into multiple regions (FIG. 2, Data Banks 0..3 of DRAM memory 115);
monitoring (FIG. 6, 605), with on-die per-region monitoring circuitry (FIG. 2, Monitor Module 114, Temp Sensors 157A; Col. 2, ll. 21-24 teach “the monitored temperature(s) may be read from temperature sensors located within the memory subsystem and uniquely associated with the various banks that make up the memory component), at least one operating parameter in each of the multiple regions (FIG. 6, 605; FIG. 3; Col. 2, ll. 30-32 teach “based on the temperature, determine temperature scaling factors for each of the banks in the multi-bank memory component”);
determining, with on-die refresh control circuitry (FIG. 2, temperature compensated memory refresh (TCMR) module 202), per-region operating parameter information from the monitoring (FIG. 6, 605, 615); and
generating, with the on-die refresh control circuitry, per-region refresh information for the multiple regions based on the per-region operating parameter information (FIG. 6, 615, 620; see FIG. 3 example thermal cases and associated refresh scaling factors; Col. 8, l. 48 – Col. 9, l. 52).
Regarding claim 14, Lo teaches the limitations of claim 10.
Lo further teaches the monitoring comprises:
at least one of
sensing an operating temperature of each of the multiple regions (FIG. 6, 605; FIG.2, Temp Sensors 157A; Col. 2, ll. 21-24 teach “the monitored temperature(s) may be read from temperature sensors located within the memory subsystem and uniquely associated with the various banks that make up the memory component);
sensing a voltage of each of the multiple regions; or
counting a number of accesses made to each of the multiple regions.
Regarding claim 15, Lo teaches the limitations of claim 10.
Lo further teaches a memory sub-system (FIG. 1, 112) including DRAM (FIG. 2, 115) under the control of a CPU (FIG. 1, 110; Col. 6, ll. 9-39).
It is inherent that any dynamic random access memory that can be controlled to store data can be said the control is carried out in accordance with “a dynamic random access memory (DRAM) protocol,” whether that protocol is proprietary, standardized, internal to a device, or external to a host (the present disclosure does not provide these details).
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 2, 5-6, 11-13, 16-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lo, et al (US 9640242 B1), hereinafter Lo, in view of Dong, et al (US 20150085594 A1), hereinafter Dong.
Regarding claim 2, Lo teaches the limitations of claim 1.
Lo does not teach the refresh circuitry refreshes each of the multiple regions during auto-refresh operations in response to refresh commands received from memory control circuitry, the refresh commands based on the per-region refresh information.
Dong teaches the refresh circuitry refreshes each of the multiple regions during auto-refresh operations in response to refresh commands received from memory control circuitry, the refresh commands based on the per-region refresh information (FIG. 4, 400, 410; ¶ [0054]; note in FIG. 1, devices 104 and 106 each have a temperature sensor uniquely associated with the various banks (memory cells 134 in device 104 and memory cells 154 in device 106) that make up the respective memory component, and so are analogous to Lo’s intra-die memory banks and temperature sensors).
Regarding claim 11, Lo teaches the limitations of claim 10.
Lo does not teach refreshing each of the multiple regions during auto-refresh operations in response to refresh commands received from memory control circuitry, the refresh commands based on the per-region refresh information.
Dong teaches refreshing each of the multiple regions during auto-refresh operations in response to refresh commands received from memory control circuitry, the refresh commands based on the per-region refresh information (FIG. 4, 400, 410; ¶ [0054]; note in FIG. 1, devices 104 and 106 each have a temperature sensor uniquely associated with the various banks (memory cells 134 in device 104 and memory cells 154 in device 106) that make up the respective memory component, and so are analogous to Lo’s intra-die memory banks and temperature sensors).
Regarding claims 2 and 11, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Dong into the method of Lo to include applying an adjusted refresh time based on specific characteristics (e.g., temperatures and retention time profile information) of memory regions rather than standardized retention times in an auto-refresh operation. The ordinary artisan would have been motivated to modify Lo in the above manner for the purpose of reducing an amount of power consumption when compared to a conventional auto-refresh memory operation (Dong, ¶ [0054]).
Regarding claim 5, Lo teaches the limitations of claim 4.
Lo does not teach the storage comprises register storage.
Dong teaches the storage comprises register storage (¶ [0005]; FIG. 1, e.g. 122, 124).
Regarding claim 12, Lo teaches the limitations of claim 10.
Lo does not teach storing the per-region refresh information in register storage.
Dong teaches storing the per-region refresh information in register storage (¶ [0005]; FIG. 1, e.g. 122, 124).
Regarding claims 5 and 12, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Dong into the method of Lo to include storing per-region refresh information in register storage. The ordinary artisan would have been motivated to modify Lo in the above manner for the purpose of utilizing dedicated storage for DRAM configuration information, which may be non-volatile (Dong ¶ [0024]).
Regarding claim 6, Lo as modified by Dong teaches the limitations of claim 5.
Dong further teaches transmit circuitry to transmit the per-region refresh information to memory control circuitry in response to a mode register read (MRR) command (¶ [0029] teaches retention time profile information, which corresponds to refresh rate (¶ [0005]), may be transmitted to the memory controller in response to an MRR command).
Regarding claim 13, Lo as modified by Dong teaches the limitations of claim 12.
Dong further teaches transmitting the per-region refresh information from the register storage to memory control circuitry in response to a mode register read (MRR) command (¶ [0029] teaches retention time profile information, which corresponds to refresh rate (¶ [0005]), may be transmitted to the memory controller in response to an MRR command).
Regarding independent claim 16, Lo teaches an integrated circuit (IC) dynamic random access memory (DRAM) device (FIG. 2, 112, part of SoC IC 102), comprising:
an array of DRAM storage cells configured into multiple refresh regions (FIG. 2, Data Banks 0..3 of DRAM memory 115; see FIG. 3 example thermal cases and associated refresh scaling factors);
monitoring circuitry coupled to each of the multiple refresh regions (FIG. 2, Monitor Module 114, Temp Sensors 157A; Col. 2, ll. 21-24 teach “the monitored temperature(s) may be read from temperature sensors located within the memory subsystem and uniquely associated with the various banks that make up the memory component, the monitoring circuitry to detect and generate per-region operating parameter information); and
refresh circuitry (FIG. 2, temperature compensated memory refresh (TCMR) module 202) to generate per-region refresh rate information for the multiple refresh regions based on the per-region operating parameter information (see FIG. 3 example thermal cases and associated refresh scaling factors; Col. 8, l. 48 – Col. 9, l. 52).
Lo does not teach mode register storage to store the per-region refresh rate information.
Dong teaches mode register storage to store the per-region refresh rate information (¶ [0005]; FIG. 1, e.g. 122, 124).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Dong into the method of Lo to include storing per-region refresh information in register storage. The ordinary artisan would have been motivated to modify Lo in the above manner for the purpose of utilizing dedicated storage for DRAM configuration information, which may be non-volatile (Dong ¶ [0024]).
Regarding claim 17, Lo as modified by Dong teaches the limitations of claim 16.
Dong further teaches transmit circuitry to transmit the per-region refresh rate information to memory control circuitry in response to a mode register read (MRR) command (¶ [0029] teaches retention time profile information, which corresponds to refresh rate (¶ [0005]), may be transmitted to the memory controller in response to an MRR command).
Regarding claim 18, Lo as modified by Dong teaches the limitations of claim 17.
Dong further teaches the refresh circuitry refreshes each of the multiple refresh regions during auto-refresh operations in response to refresh commands received from the memory control circuitry, the refresh commands based on the per-region refresh rate information (FIG. 4, 400, 410; ¶ [0054]; note in FIG. 1, devices 104 and 106 each have a temperature sensor uniquely associated with the various banks (memory cells 134 in device 104 and memory cells 154 in device 106) that make up the memory component, and so are analogous to Lo’s intra-die memory banks and temperature sensors).
Regarding claim 20, Lo as modified by Dong teaches the limitations of claim 16.
Lo further teaches the refresh circuitry generates the per-region refresh rate information as representations of relative refresh rates for the multiple refresh regions (FIG. 3 and Col. 1, ll. 26-61 teach a scaling factor that acts as a multiplier for a baseline refresh cycle time, and so each scaling factor represents a value relative to the baseline).
8. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lo, et al (US 9640242 B1), hereinafter Lo, in view of Dally (US 9224449 B2).
Regarding claim 8, Lo teaches the limitations of claim 1.
Lo does not teach the refresh circuitry generates the per-region refresh information as representations of absolute refresh rates for the multiple regions.
Dally teaches the refresh circuitry generates the per-region refresh information as representations of absolute refresh rates for the multiple regions (Col. 5, ll. 46-48 teach the refresh intervals stored in the refresh table 265 are initialized to equal the refresh interval specified by the DRAM supplier. Col. 4, ll. 16-64 teach the refresh intervals for a memory region may then be adjusted by multiples of two (e.g., from 64ms to 128ms, etc.) based on characterization during operation and may be based on temperature.).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Dally into the method of Lo to include generating per-region refresh rate information as representations of absolute refresh rates. The ordinary artisan would have been motivated to modify Lo in the above manner for the purpose of using manufacturer specifications/recommendations as a baseline refresh rate to be adjusted during operation (Dally, Col. 2, ll. 23-26; Col. 5, ll. 46-48; Col. 4, ll. 16-64).
9. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lo, et al (US 9640242 B1), hereinafter Lo, in view of Dong, et al (US 20150085594 A1), hereinafter Dong, and further in view of Dally (US 9224449 B2).
Regarding claim 19, Lo as modified by Dong teaches the limitations of claim 16.
Lo does not teach the refresh circuitry generates the per-region refresh rate information as representations of absolute refresh rates for the multiple regions.
Dally teaches the refresh circuitry generates the per-region refresh rate information as representations of absolute refresh rates for the multiple regions (Col. 5, ll. 46-48 teach the refresh intervals stored in the refresh table 265 are initialized to equal the refresh interval specified by the DRAM supplier. Col. 4, ll. 16-64 teach the refresh intervals for a memory region may then be adjusted by multiples of two (e.g., from 64ms to 128ms, etc.) based on characterization during operation and may be based on temperature.).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Dally into the method of Lo to include generating per-region refresh rate information as representations of absolute refresh rates. The ordinary artisan would have been motivated to modify Lo in the above manner for the purpose of using manufacturer specifications/recommendations as a baseline refresh rate to be adjusted during operation (Dally, Col. 2, ll. 23-26; Col. 5, ll. 46-48; Col. 4, ll. 16-64).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827