Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Mueller et al. [US PGUB 20190057950] in view of Fukahori et al. [US PGPUB 20190214815] (hereinafter Mueller and Fukahori).
Regarding claim 1, Mueller discloses a semiconductor device, comprising:
a device wafer (404, Para 32, Fig. 4C, i.e., wafer for device layer 402) including a first and a second sides opposite to each other (Fig. 4C, side facing 403/411 and side facing 402 respectively); and
a carrier wafer (411/413, Fig. 4C) disposed over the first side of the device wafer (Fig. 4C) and comprising a protection circuit (437/438, Para 32, Fig. 4C), the protection circuit comprising a first diode (438, Para 32),
wherein the first diode is operatively coupled to a first power rail (left pad of 414, Fig. 4C; i.e., due to its connection to bump 416 which provides power to the diode, Para 32) at least through the device wafer, and a second power rail (right pad of 414, Fig. 4C; i.e., due to its connection to bump 416 which provides power to the diode, Para 32).
Mueller does not specifically disclose that the protection circuit is an electrostatic discharge (ESD) protection circuit;
the ESD protection circuit comprising a second diode;
the ESD protection circuit comprising a second diode; and
wherein the second diode are is operatively coupled to a second power rail at least through the device wafer.
However, it is noted that Mueller invention is related to controlling electrostatic discharge in a structure for an electronic device (Para 14/16-17).
Referring to the invention of Fukahori, Fukahori teaches implementing a diode and a capacitor as an electrostatic discharge (ESD) protection circuit (Para 2).
Fukahori further discloses various ESD protection devices, wherein in an instance (Fig. 13/14), instead of one electrostatic discharge (ESD) protection circuit, two electrostatic discharge (ESD) protection circuit were implemented.
Thus, in implementing two electrostatic discharge (ESD) protection circuit in Mueller’s invention, structure 437 and 438 of Mueller would be individually replaced with an electrostatic discharge (ESD) protection circuit (i.e., structure 437 of Mueller replace with D2A & C1 of Fukahori and replace structure 438 of Mueller replace with D1A & C2 of Fukahori).
In view of such teaching by Fukahori, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have circuit (diode 438 and capacitor 437) in the device of Mueller coupled or function as an electrostatic discharge (ESD) protection circuit as taught by Fukahori in order to prevent damage to the device being produced.
Furthermore, in view of the teaching of implementing two electrostatic discharge (ESD) protection circuit instead of just one electrostatic discharge (ESD) protection circuit, it would have been obvious to a person having ordinary skills in the art to have each power rail of Mueller have its own electrostatic discharge (ESD) protection circuit (thus, two diodes), in order to localize static discharge.
Regarding claim 2, Mueller discloses a semiconductor device further comprising a plurality of first interconnect structures (436s in layer 403, Para 32, Fig. 4C) disposed on the first side of the device wafer and under the carrier wafer (Fig. 4C).
Regarding claim 3, Mueller discloses a semiconductor device wherein the first diode is operatively coupled to the first power rail and the second diode is operatively coupled to the second power rail through at least one or more of the plurality of first interconnect structures (Fig. 4C).
Regarding claim 4 the modified invention of Mueller specifically in view of Fukahori teaches a semiconductor device wherein the first diode has a first terminal connected to the first power rail that is configured to carry VDD (Fukahori, Fig. 14, connected to P1), and the second diode has a first terminal connected to the second power rail that is configured to carry VSS (Fukahori , Fig. 14, connected to GP).
Regarding claim 9, Mueller discloses a semiconductor device wherein the first power rail and the second power rail are formed on the second side of the device wafer (Fig. 4C).
Regarding claim 17, Mueller discloses a method for making a semiconductor device, comprising:
forming a plurality of interconnect structures (436s in layer 403, Para 32, Fig. 4C) over a first side of a device wafer (404, Para 32, Fig. 4C, i.e., wafer for device layer 402);
forming a carrier wafer (411/413, Fig. 4C) over the plurality of interconnect structures and having a first side facing the first side of the device wafer (Fig. 4C), the carrier wafer comprising an protection circuit (437/438, Para 32, Fig. 4C) comprising a first diode (438, Para 32, Fig. 4C);
coupling the first side of the device wafer to the first side of the carrier wafer (Fig. 4A/C);
forming a first power rail (left pad of 414, Fig. 4C; i.e., due to its connection to bump 416 which provides power to the diode, Para 32) and a second power rail (right pad of 414, Fig. 4C; i.e., due to its connection to bump 416 which provides power to the diode, Para 32) over a second side of the device wafer opposite to the first side of the device wafer (Fig. 4C); and
coupling the first diode to the first power rail (Fig. 4C) through at least one of the plurality of interconnect structures (Fig. 4C).
Mueller does not specifically disclose that the protection circuit is an electrostatic discharge (ESD) protection circuit;
a second diode; and
coupling the second diode to the second power rail through at least one of the plurality of interconnect structures, the first power rail and the second power rail having opposite potentials.
However, it is noted that Mueller invention is related to controlling electrostatic discharge in a structure for an electronic device (Para 14/16-17).
Referring to the invention of Fukahori, Fukahori teaches implementing a diode and a capacitor as an electrostatic discharge (ESD) protection circuit (Para 2).
Fukahori further discloses various ESD protection devices, wherein in an instance (Fig. 13/14), instead of one electrostatic discharge (ESD) protection circuit, two electrostatic discharge (ESD) protection circuit were implemented; wherein each D1A and D2A are connected to first power rail P1/P2 (input (high)) and second power rail (GP, ground (low))
Thus, in implementing two electrostatic discharge (ESD) protection circuit in Mueller’s invention, structure 437 and 438 of Mueller would be individually replaced with an electrostatic discharge (ESD) protection circuit (i.e., structure 437 of Mueller replace with D2A & C1 of Fukahori and replace structure 438 of Mueller replace with D1A & C2 of Fukahori).
In view of such teaching by Fukahori, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have circuit (diode 438 and capacitor 437) in the device of Mueller coupled or function as an electrostatic discharge (ESD) protection circuit as taught by Fukahori in order to prevent damage to the device being produced.
Furthermore, in view of the teaching of implementing two electrostatic discharge (ESD) protection circuit instead of just one electrostatic discharge (ESD) protection circuit, it would have been obvious to a person having ordinary skills in the art to have each power rail of Mueller have its own electrostatic discharge (ESD) protection circuit (thus, two diodes), in order to localize static discharge.
In view of such modification, a person having ordinary skills in the art would find it obvious that the limitations of claim 17 have been met.
Allowable Subject Matter
Claims 10-16 allowed.
Claims 5-8 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 10-16 are allowed because all prior arts of record and related prior arts not of record either singularly or in combination fail to anticipate or render obvious a semiconductor device, comprising:
wherein the carrier wafer comprises an electrostatic discharge (ESD) protection circuit on the second side of the carrier wafer,
wherein the device wafer comprises a first power rail and a second power rail on the second side of the device wafer (as claimed in claim 10), in combination with the rest of claim limitations as claimed and defined by the Applicant.
. Conclusion
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/ISMAIL A MUSE/Primary Examiner, Art Unit 2812
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