Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/16/2025 has been entered.
Obvious Double Patenting Withdrawal
Applicant’s amendment of Claims 1 and 16 is acknowledged. Thus, the obvious double patenting is withdrawn.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 16 rejected under 35 U.S.C. 103 as being unpatentable over Noguchi (U.S. Patent Pub. No. 2012/0127220) of record, in view of Han (U.S. Patent Pub. No. 2012/0019504) of record, in view of Chae (CN 100511698, machine-translation provided)
Regarding Claim 1
FIGS. 7-9 of Noguchi disclose a display device comprising: a substrate (100); a first active pattern (101) disposed on the substrate, the first active pattern including a first region (shared S/D of T4 and T3/T5), a second region (shared S/D of T4 and T2), a third region (shared S/D of T2 and T1), and a fourth region (shared S/D of upper T2 and lower T2); a first lower gate electrode (102, gate of T4) disposed on the first active pattern, the first lower gate electrode defining a first transistor (T4) together with the first (S/D of T4, connected with S/D of T3 and T5) and second regions (S/D of T4, connected with S/D of lower T2) by partially overlapping the first active pattern (FIG. 9); a first gate electrode (gate of T2) spaced apart from the first lower gate electrode (102), the first gate electrode defining a second transistor (upper T2) together with the third (shared S/D of T2 and T1) and fourth regions (shared S/D of upper T2 and lower T2) and defining a third transistor (lower T2) together with the fourth and second regions (shared S/D of T4 and lower T2) by partially overlapping the first active pattern; a second conductive pattern (upper electrode of C1 connecting ELVDD) defining a storage capacitor (C1) together with the first lower gate electrode (102) by partially overlapping the first lower gate electrode (FIG. 8); and a first light-emitting layer (OLED) disposed on the first-first and second-first conductive patterns and the second conductive pattern; and a first light-emitting layer (above 103) disposed on the substrate (100, FIG. 9).
Noguchi fails to disclose “a first gate electrode spaced apart from the first lower gate electrode on a same layer”; “a first-first conductive pattern disposed on the first gate electrode and the first lower gate electrode, the first-first conductive pattern defining a first capacitor together with the fourth region by partially overlapping the first active pattern in a thickness direction of the substrate”; “a second-first conductive pattern spaced apart from the first-first conductive pattern on a same layer, the second-first conductive pattern defining a second capacitor together with the third region by partially overlapping the first active pattern in the thickness direction of the substrate”; “a first power supply voltage is provided to both the first-first conductive pattern and the second-first conductive pattern” and “the first-first conductive pattern corresponding to the fourth region is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate”.
FIG. 2 of Han discloses a similar display device, comprising a second capacitor (C1) and a first capacitor (C2) such that the voltages of the first node N1, the second node N2, and the third node N3 are set as the same, thereby minimizing or reducing the leakage currents that flow to the second node N2 and the third node N3 from the first node N1 [0058]; the display device comprises a first-first conductive pattern (upper electrode of C2, connecting to ELVDD) and a second-first conductive pattern (upper electrode of C1 connecting to ELVDD) spaced apart from the first conductive pattern, wherein the first-first conductive pattern defining a first capacitor (C2) together with the fourth region (shared S/D of M3-1 and M3-2, where M3-1 = upper T2 of Noguchi, M3-2 = lower T2 of Noguchi) by partially overlapping the first active pattern (the fourth region as lower electrode of C2); the second-first conductive pattern defining a second capacitor (C1) together with the third region (shared S/D of M3-1 and M4-1, connecting the gate of M1, where M3-1 = upper T2 of Noguchi, M4-1 = T1 of Noguchi, M1 = T4 of Noguchi) by partially overlapping the first active pattern (the third region as the lower electrode of C1).
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Han, such that a second capacitor and a first capacitor are added to minimize or reduce the leakage currents [0058], thereby displaying the image of the desired luminance [0022]. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of minimizing leakage current (Para. 58 of Han).
Noguchi as modified by Han discloses the upper electrodes of the first capacitor, the second capacitor, and the storage capacitor are portions of a power supply voltage line, therefore, the first-first conductive pattern, the second-first conductive pattern, and the second conductive pattern are on a same layer; and a first light-emitting layer disposed on the first-first and second-first conductive patterns and the second conductive pattern.
Noguchi as modified by Han fails to explicitly disclose the “first-first conductive pattern disposed on the first gate electrode and the first lower gate electrode”; the first-first conductive pattern “partially overlapping the first active pattern in a thickness direction of the substrate”; the second-first conductive pattern “partially overlapping the first active pattern in the thickness direction of the substrate”; “a first power supply voltage is provided to both the first-first conductive pattern and the second-first conductive pattern” and “the first-first conductive pattern corresponding to the fourth region is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate”.
FIG. 7C of Chae discloses a similar display device, comprising a first lower gate electrode (108’); a first gate electrode (108) spaced apart from the first lower gate electrode on a same layer; a first-first conductive pattern (116’ above 113) disposed the first lower gate electrode; a second-first conductive pattern (116 above 113) on a same layer and partially overlapping the first active pattern (104’) in the thickness direction (vertical) of the substrate, and a first power supply voltage (112) is provided to both the first-first conductive pattern and the second-first conductive pattern, wherein the first-first conductive pattern corresponding to the fourth region (105’) is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Chae. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of reducing the probability of circuit defect (Page 8 of Chae).
Regarding Claim 16
FIGS. 7-9 of Noguchi disclose an electronic device comprising: a display device configured to display an image; and an image processor configured to render the image, wherein the display device includes: a substrate (100); a first active pattern disposed on the substrate, the first active pattern including a first region (shared S/D of T4 and T3/T5), a second region (shared S/D of T4 and T2), a third region (shared S/D of T2 and T1), and a fourth region (shared S/D of upper T2 and lower T2); a first lower gate electrode (102, gate of T4) disposed on the first active pattern, the first lower gate electrode defining a first transistor (T4) together with the first (S/D of T4, connected with S/D of T3 and T5) and second regions (S/D of T4, connected with S/D of lower T2) by partially overlapping the first active pattern (FIG. 9); a first gate electrode (gate of T2) spaced apart from the first lower gate electrode (102), the first gate electrode defining a second transistor (upper T2) together with the third (shared S/D of T2 and T1) and fourth regions (shared S/D of upper T2 and lower T2) and defining a third transistor (lower T2) together with the fourth and second regions (shared S/D of T4 and lower T2) by partially overlapping the first active pattern; a second conductive pattern (upper electrode of C1 connecting ELVDD) defining a storage capacitor (C1) together with the first lower gate electrode (102) by partially overlapping the first lower gate electrode (FIG. 8); and a first light-emitting layer (OLED) disposed on the first-first and second-first conductive patterns and the second conductive pattern; and a first light-emitting layer (above 103) disposed on the substrate (100, FIG. 9).
Noguchi fails to disclose “a first gate electrode spaced apart from the first lower gate electrode on a same layer”; “a first-first conductive pattern disposed on the first gate electrode and the first lower gate electrode, the first-first conductive pattern defining a first capacitor together with the fourth region by partially overlapping the first active pattern in a thickness direction of the substrate”; “a second-first conductive pattern spaced apart from the first-first conductive pattern on a same layer, the second-first conductive pattern defining a second capacitor together with the third region by partially overlapping the first active pattern in the thickness direction of the substrate”; and “a first power supply voltage is provided to both the first-first conductive pattern and the second-first conductive pattern” and “the first-first conductive pattern corresponding to the fourth region is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate”.
FIG. 2 of Han discloses a similar display device, comprising a second capacitor (C1) and a first capacitor (C2) such that the voltages of the first node N1, the second node N2, and the third node N3 are set as the same, thereby minimizing or reducing the leakage currents that flow to the second node N2 and the third node N3 from the first node N1 [0058]; the display device comprises a first-first conductive pattern (upper electrode of C2, connecting to ELVDD) and a second-first conductive pattern (upper electrode of C1 connecting to ELVDD) spaced apart from the first conductive pattern, wherein the first-first conductive pattern defining a first capacitor (C2) together with the fourth region (shared S/D of M3-1 and M3-2, where M3-1 = upper T2 of Noguchi, M3-2 = lower T2 of Noguchi) by partially overlapping the first active pattern (the fourth region as lower electrode of C2); the second-first conductive pattern defining a second capacitor (C1) together with the third region (shared S/D of M3-1 and M4-1, connecting the gate of M1, where M3-1 = upper T2 of Noguchi, M4-1 = T1 of Noguchi, M1 = T4 of Noguchi) by partially overlapping the first active pattern (the third region as the lower electrode of C1).
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Han, such that a second capacitor and a first capacitor are added to minimize or reduce the leakage currents [0058], thereby displaying the image of the desired luminance [0022]. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of minimizing leakage current (Para. 58 of Han).
Noguchi as modified by Han discloses the upper electrodes of the first capacitor, the second capacitor, and the storage capacitor are portions of a power supply voltage line, therefore, the first-first conductive pattern, the second-first conductive pattern, and the second conductive pattern are on a same layer; and a first light-emitting layer disposed on the first-first and second-first conductive patterns and the second conductive pattern.
Noguchi as modified by Han fails to explicitly disclose “a first gate electrode spaced apart from the first lower gate electrode on a same layer”; the “first-first conductive pattern disposed on the first gate electrode and the first lower gate electrode”; the first-first conductive pattern “partially overlapping the first active pattern in a thickness direction of the substrate”; the second-first conductive pattern “partially overlapping the first active pattern in the thickness direction of the substrate”; “a first power supply voltage is provided to both the first-first conductive pattern and the second-first conductive pattern” and “the first-first conductive pattern corresponding to the fourth region is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate”.
FIG. 7 of Chae discloses a similar display device, comprising a first lower gate electrode (108’); a first gate electrode (108) spaced apart from the first lower gate electrode on a same layer; a first-first conductive pattern (116’ above 113) disposed the first lower gate electrode; a second-first conductive pattern (116 above 113) on a same layer and partially overlapping the first active pattern (104’) in the thickness direction (vertical) of the substrate, and a first power supply voltage (112) is provided to both the first-first conductive pattern and the second-first conductive pattern, wherein the first-first conductive pattern corresponding to the fourth region (105’) is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Chae. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of reducing the probability of circuit defect (Page 8 of Chae).
Claims 1 and 16 rejected under 35 U.S.C. 103 as being unpatentable over Noguchi, in view of Han (U.S. Patent Pub. No. 2012/0019504) of record, in view of Koiwa (U.S. Patent Pub. No. 2006/0221520) of record, in view of Yamauchi (U.S. Patent No. 6,512,504)
Regarding Claim 1
FIGS. 7-9 of Noguchi disclose a display device comprising: a substrate (100); a first active pattern (101) disposed on the substrate, the first active pattern including a first region (shared S/D of T4 and T3/T5), a second region (shared S/D of T4 and T2), a third region (shared S/D of T2 and T1), and a fourth region (shared S/D of upper T2 and lower T2); a first lower gate electrode (102, gate of T4) disposed on the first active pattern, the first lower gate electrode defining a first transistor (T4) together with the first (S/D of T4, connected with S/D of T3 and T5) and second regions (S/D of T4, connected with S/D of lower T2) by partially overlapping the first active pattern (FIG. 9); a first gate electrode (gate of T2) spaced apart from the first lower gate electrode (102), the first gate electrode defining a second transistor (upper T2) together with the third (shared S/D of T2 and T1) and fourth regions (shared S/D of upper T2 and lower T2) and defining a third transistor (lower T2) together with the fourth and second regions (shared S/D of T4 and lower T2) by partially overlapping the first active pattern; a second conductive pattern (upper electrode of C1 connecting ELVDD) defining a storage capacitor (C1) together with the first lower gate electrode (102) by partially overlapping the first lower gate electrode (FIG. 8); and a first light-emitting layer (OLED) disposed on the first-first and second-first conductive patterns and the second conductive pattern; and a first light-emitting layer (above 103) disposed on the substrate (100, FIG. 9).
Noguchi fails to disclose “a first gate electrode spaced apart from the first lower gate electrode on a same layer”; “a first-first conductive pattern disposed on the first gate electrode and the first lower gate electrode, the first-first conductive pattern defining a first capacitor together with the fourth region by partially overlapping the first active pattern in a thickness direction of the substrate”; “a second-first conductive pattern spaced apart from the first-first conductive pattern on a same layer, the second-first conductive pattern defining a second capacitor together with the third region by partially overlapping the first active pattern in the thickness direction of the substrate”; “a first power supply voltage is provided to both the first-first conductive pattern and the second-first conductive pattern” and “the first-first conductive pattern corresponding to the fourth region is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate”.
FIG. 2 of Han discloses a similar display device, comprising a second capacitor (C1) and a first capacitor (C2) such that the voltages of the first node N1, the second node N2, and the third node N3 are set as the same, thereby minimizing or reducing the leakage currents that flow to the second node N2 and the third node N3 from the first node N1 [0058]; the display device comprises a first-first conductive pattern (upper electrode of C2, connecting to ELVDD) and a second-first conductive pattern (upper electrode of C1 connecting to ELVDD) spaced apart from the first conductive pattern, wherein the first-first conductive pattern defining a first capacitor (C2) together with the fourth region (shared S/D of M3-1 and M3-2, where M3-1 = upper T2 of Noguchi, M3-2 = lower T2 of Noguchi) by partially overlapping the first active pattern (the fourth region as lower electrode of C2); the second-first conductive pattern defining a second capacitor (C1) together with the third region (shared S/D of M3-1 and M4-1, connecting the gate of M1, where M3-1 = upper T2 of Noguchi, M4-1 = T1 of Noguchi, M1 = T4 of Noguchi) by partially overlapping the first active pattern (the third region as the lower electrode of C1).
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Han, such that a second capacitor and a first capacitor are added to minimize or reduce the leakage currents [0058], thereby displaying the image of the desired luminance [0022]. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of minimizing leakage current (Para. 58 of Han).
Noguchi as modified by Han discloses the upper electrodes of the first capacitor, the second capacitor, and the storage capacitor are portions of a power supply voltage line, therefore, the first-first conductive pattern, the second-first conductive pattern, and the second conductive pattern are on a same layer; and a first light-emitting layer disposed on the first-first and second-first conductive patterns and the second conductive pattern.
Noguchi as modified by Han fails to explicitly disclose “a first gate electrode spaced apart from the first lower gate electrode on a same layer”; the “first-first conductive pattern disposed on the first gate electrode and the first lower gate electrode”; the first-first conductive pattern “partially overlapping the first active pattern in a thickness direction of the substrate”; the second-first conductive pattern “partially overlapping the first active pattern in the thickness direction of the substrate”; “a first power supply voltage is provided to both the first-first conductive pattern and the second-first conductive pattern” and “the first-first conductive pattern corresponding to the fourth region is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate”.
FIG. 3 of Koiwa discloses a similar display device, comprising a first gate electrode (2b) spaced apart from the first lower gate electrode (2a) on a same layer; a first-first conductive pattern (6d, as upper electrode of the second capacitor, equivalent to 150 of the application FIG. 10) disposed on the first gate electrode and the first lower gate electrode; a second-first conductive pattern (6c, as upper electrode of the first capacitor, equivalent to 130 of the application FIG. 10) on a same layer and partially overlapping the first active pattern (7b) in the thickness direction (vertical) of the substrate, and a first power supply voltage [0045] is provided to both the first-first conductive pattern and the second-first conductive pattern, wherein the first-first conductive pattern is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Koiwa. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of improving operation speed and packing density (Para. 7 of Koiwa).
Noguchi as modified by Han and Koiwa fails to explicitly disclose “the first-first conductive pattern corresponding to the fourth region”.
FIG. 1 of Yamauchi discloses a similar display device, comprising a first gate electrode (19b) spaced apart from the first lower gate electrode (19a) on a same layer; a first-first conductive pattern (25) disposed on the first gate electrode and the first lower gate electrode; wherein the first-first conductive pattern corresponding to the fourth region (23) is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Yamauchi. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of improving operational performance and reliability (Abstract of Yamauchi).
Regarding Claim 16
FIGS. 7-9 of Noguchi disclose an electronic device comprising: a display device configured to display an image; and an image processor configured to render the image, wherein the display device includes: a substrate (100); a first active pattern disposed on the substrate, the first active pattern including a first region (shared S/D of T4 and T3/T5), a second region (shared S/D of T4 and T2), a third region (shared S/D of T2 and T1), and a fourth region (shared S/D of upper T2 and lower T2); a first lower gate electrode (102, gate of T4) disposed on the first active pattern, the first lower gate electrode defining a first transistor (T4) together with the first (S/D of T4, connected with S/D of T3 and T5) and second regions (S/D of T4, connected with S/D of lower T2) by partially overlapping the first active pattern (FIG. 9); a first gate electrode (gate of T2) spaced apart from the first lower gate electrode (102), the first gate electrode defining a second transistor (upper T2) together with the third (shared S/D of T2 and T1) and fourth regions (shared S/D of upper T2 and lower T2) and defining a third transistor (lower T2) together with the fourth and second regions (shared S/D of T4 and lower T2) by partially overlapping the first active pattern; a second conductive pattern (upper electrode of C1 connecting ELVDD) defining a storage capacitor (C1) together with the first lower gate electrode (102) by partially overlapping the first lower gate electrode (FIG. 8); and a first light-emitting layer (OLED) disposed on the first-first and second-first conductive patterns and the second conductive pattern; and a first light-emitting layer (above 103) disposed on the substrate (100, FIG. 9).
Noguchi fails to disclose “a first gate electrode spaced apart from the first lower gate electrode on a same layer”; “a first-first conductive pattern disposed on the first gate electrode and the first lower gate electrode, the first-first conductive pattern defining a first capacitor together with the fourth region by partially overlapping the first active pattern in a thickness direction of the substrate”; “a second-first conductive pattern spaced apart from the first-first conductive pattern on a same layer, the second-first conductive pattern defining a second capacitor together with the third region by partially overlapping the first active pattern in the thickness direction of the substrate”; and “a first power supply voltage is provided to both the first-first conductive pattern and the second-first conductive pattern” and “the first-first conductive pattern corresponding to the fourth region is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate”.
FIG. 2 of Han discloses a similar display device, comprising a second capacitor (C1) and a first capacitor (C2) such that the voltages of the first node N1, the second node N2, and the third node N3 are set as the same, thereby minimizing or reducing the leakage currents that flow to the second node N2 and the third node N3 from the first node N1 [0058]; the display device comprises a first-first conductive pattern (upper electrode of C2, connecting to ELVDD) and a second-first conductive pattern (upper electrode of C1 connecting to ELVDD) spaced apart from the first conductive pattern, wherein the first-first conductive pattern defining a first capacitor (C2) together with the fourth region (shared S/D of M3-1 and M3-2, where M3-1 = upper T2 of Noguchi, M3-2 = lower T2 of Noguchi) by partially overlapping the first active pattern (the fourth region as lower electrode of C2); the second-first conductive pattern defining a second capacitor (C1) together with the third region (shared S/D of M3-1 and M4-1, connecting the gate of M1, where M3-1 = upper T2 of Noguchi, M4-1 = T1 of Noguchi, M1 = T4 of Noguchi) by partially overlapping the first active pattern (the third region as the lower electrode of C1).
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Han, such that a second capacitor and a first capacitor are added to minimize or reduce the leakage currents [0058], thereby displaying the image of the desired luminance [0022]. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of minimizing leakage current (Para. 58 of Han).
Noguchi as modified by Han discloses the upper electrodes of the first capacitor, the second capacitor, and the storage capacitor are portions of a power supply voltage line, therefore, the first-first conductive pattern, the second-first conductive pattern, and the second conductive pattern are on a same layer; and a first light-emitting layer disposed on the first-first and second-first conductive patterns and the second conductive pattern.
Noguchi as modified by Han fails to explicitly disclose “a first gate electrode spaced apart from the first lower gate electrode on a same layer”; the “first-first conductive pattern disposed on the first gate electrode and the first lower gate electrode”; the first-first conductive pattern “partially overlapping the first active pattern in a thickness direction of the substrate”; the second-first conductive pattern “partially overlapping the first active pattern in the thickness direction of the substrate”; “a first power supply voltage is provided to both the first-first conductive pattern and the second-first conductive pattern” and “the first-first conductive pattern corresponding to the fourth region is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate”.
FIG. 3 of Koiwa discloses a similar display device, comprising a first gate electrode (2b) spaced apart from the first lower gate electrode (2a) on a same layer; a first-first conductive pattern (6d, as upper electrode of the second capacitor, equivalent to 150 of the application FIG. 10) disposed on the first gate electrode and the first lower gate electrode; a second-first conductive pattern (6c, as upper electrode of the first capacitor, equivalent to 130 of the application FIG. 10) on a same layer and partially overlapping the first active pattern (7b) in the thickness direction (vertical) of the substrate, and a first power supply voltage [0045] is provided to both the first-first conductive pattern and the second-first conductive pattern, wherein the first-first conductive pattern is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Koiwa. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of improving operation speed and packing density (Para. 7 of Koiwa).
Noguchi as modified by Han and Koiwa fails to explicitly disclose “the first-first conductive pattern corresponding to the fourth region”.
FIG. 1 of Yamauchi discloses a similar display device, comprising a first gate electrode (19b) spaced apart from the first lower gate electrode (19a) on a same layer; a first-first conductive pattern (25) disposed on the first gate electrode and the first lower gate electrode; wherein the first-first conductive pattern corresponding to the fourth region (23) is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Yamauchi. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of improving operational performance and reliability (Abstract of Yamauchi).
Claims 1, 2 ,16 and 17 rejected under 35 U.S.C. 103 as being unpatentable over Noguchi (U.S. Patent Pub. No. 2012/0127220) of record, in view of Han (U.S. Patent Pub. No. 2012/0019504) of record, in view of Wen (U.S. Patent Pub. No. 2014/0110787) of record.
Regarding Claim 1
FIGS. 7-9 of Noguchi disclose a display device comprising: a substrate (100); a first active pattern (101) disposed on the substrate, the first active pattern including a first region (shared S/D of T4 and T3/T5), a second region (shared S/D of T4 and T2), a third region (shared S/D of T2 and T1), and a fourth region (shared S/D of upper T2 and lower T2); a first lower gate electrode (102, gate of T4) disposed on the first active pattern, the first lower gate electrode defining a first transistor (T4) together with the first (S/D of T4, connected with S/D of T3 and T5) and second regions (S/D of T4, connected with S/D of lower T2) by partially overlapping the first active pattern (FIG. 9); a first gate electrode (gate of T2) spaced apart from the first lower gate electrode (102), the first gate electrode defining a second transistor (upper T2) together with the third (shared S/D of T2 and T1) and fourth regions (shared S/D of upper T2 and lower T2) and defining a third transistor (lower T2) together with the fourth and second regions (shared S/D of T4 and lower T2) by partially overlapping the first active pattern; a second conductive pattern (upper electrode of C1 connecting ELVDD) defining a storage capacitor (C1) together with the first lower gate electrode (102) by partially overlapping the first lower gate electrode (FIG. 8); and a first light-emitting layer (OLED) disposed on the first-first and second-first conductive patterns and the second conductive pattern; and a first light-emitting layer (above 103) disposed on the substrate (100, FIG. 9).
Noguchi fails to disclose “a first gate electrode spaced apart from the first lower gate electrode on a same layer”; “a first-first conductive pattern disposed on the first gate electrode and the first lower gate electrode, the first-first conductive pattern defining a first capacitor together with the fourth region by partially overlapping the first active pattern in a thickness direction of the substrate”; “a second-first conductive pattern spaced apart from the first-first conductive pattern on a same layer, the second-first conductive pattern defining a second capacitor together with the third region by partially overlapping the first active pattern in the thickness direction of the substrate”; “a first power supply voltage is provided to both the first-first conductive pattern and the second-first conductive pattern” and “the first-first conductive pattern corresponding to the fourth region is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate”.
FIG. 2 of Han discloses a similar display device, comprising a second capacitor (C1) and a first capacitor (C2) such that the voltages of the first node N1, the second node N2, and the third node N3 are set as the same, thereby minimizing or reducing the leakage currents that flow to the second node N2 and the third node N3 from the first node N1 [0058]; the display device comprises a first-first conductive pattern (upper electrode of C2, connecting to ELVDD) and a second-first conductive pattern (upper electrode of C1 connecting to ELVDD) spaced apart from the first conductive pattern, wherein the first-first conductive pattern defining a first capacitor (C2) together with the fourth region (shared S/D of M3-1 and M3-2, where M3-1 = upper T2 of Noguchi, M3-2 = lower T2 of Noguchi) by partially overlapping the first active pattern (the fourth region as lower electrode of C2); the second-first conductive pattern defining a second capacitor (C1) together with the third region (shared S/D of M3-1 and M4-1, connecting the gate of M1, where M3-1 = upper T2 of Noguchi, M4-1 = T1 of Noguchi, M1 = T4 of Noguchi) by partially overlapping the first active pattern (the third region as the lower electrode of C1).
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Han, such that a second capacitor and a first capacitor are added to minimize or reduce the leakage currents [0058], thereby displaying the image of the desired luminance [0022]. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of minimizing leakage current (Para. 58 of Han).
Noguchi as modified by Han discloses the upper electrodes of the first capacitor, the second capacitor, and the storage capacitor are portions of a power supply voltage line, therefore, the first-first conductive pattern, the second-first conductive pattern, and the second conductive pattern are on a same layer; and a first light-emitting layer disposed on the first-first and second-first conductive patterns and the second conductive pattern.
Noguchi as modified by Han fails to explicitly disclose “a first gate electrode spaced apart from the first lower gate electrode on a same layer”; the “first-first conductive pattern disposed on the first gate electrode and the first lower gate electrode”; the first-first conductive pattern “partially overlapping the first active pattern in a thickness direction of the substrate”; the second-first conductive pattern “partially overlapping the first active pattern in the thickness direction of the substrate”; “a first power supply voltage is provided to both the first-first conductive pattern and the second-first conductive pattern” and “the first-first conductive pattern corresponding to the fourth region is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate”.
FIG. 6 (annotated below) of Wen discloses a similar display device, comprising a first gate electrode (G1) spaced apart from the first lower gate electrode (LG) on a same layer; a first-first conductive pattern (w11) disposed on the first gate electrode and the first lower gate electrode; a second-first conductive pattern (w12) on a same layer and partially overlapping the first active pattern in the thickness direction (vertical) of the substrate, and a first power supply voltage [0023] is provided to both the first-first conductive pattern and the second-first conductive pattern, wherein the first capacitor and the second capacitor are parasitic capacitors, and wherein the first-first conductive pattern corresponding to the fourth region (a4) is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Wen. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of forming cascade MOS devices (Para. 1 of Wen).
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Regarding Claim 2
FIG. 6 of Wen discloses the first-first conductive pattern corresponding to the fourth region is spaced apart from any other electrodes both in the thickness direction of the substrate and in the direction perpendicular to the thickness direction of the substrate.
Regarding Claim 16
FIGS. 7-9 of Noguchi disclose an electronic device comprising: a display device configured to display an image; and an image processor configured to render the image, wherein the display device includes: a substrate (100); a first active pattern disposed on the substrate, the first active pattern including a first region (shared S/D of T4 and T3/T5), a second region (shared S/D of T4 and T2), a third region (shared S/D of T2 and T1), and a fourth region (shared S/D of upper T2 and lower T2); a first lower gate electrode (102, gate of T4) disposed on the first active pattern, the first lower gate electrode defining a first transistor (T4) together with the first (S/D of T4, connected with S/D of T3 and T5) and second regions (S/D of T4, connected with S/D of lower T2) by partially overlapping the first active pattern (FIG. 9); a first gate electrode (gate of T2) spaced apart from the first lower gate electrode (102), the first gate electrode defining a second transistor (upper T2) together with the third (shared S/D of T2 and T1) and fourth regions (shared S/D of upper T2 and lower T2) and defining a third transistor (lower T2) together with the fourth and second regions (shared S/D of T4 and lower T2) by partially overlapping the first active pattern; a second conductive pattern (upper electrode of C1 connecting ELVDD) defining a storage capacitor (C1) together with the first lower gate electrode (102) by partially overlapping the first lower gate electrode (FIG. 8); and a first light-emitting layer (OLED) disposed on the first-first and second-first conductive patterns and the second conductive pattern; and a first light-emitting layer (above 103) disposed on the substrate (100, FIG. 9).
Noguchi fails to disclose “a first gate electrode spaced apart from the first lower gate electrode on a same layer”; “a first-first conductive pattern disposed on the first gate electrode and the first lower gate electrode, the first-first conductive pattern defining a first capacitor together with the fourth region by partially overlapping the first active pattern in a thickness direction of the substrate”; “a second-first conductive pattern spaced apart from the first-first conductive pattern on a same layer, the second-first conductive pattern defining a second capacitor together with the third region by partially overlapping the first active pattern in the thickness direction of the substrate”; and “a first power supply voltage is provided to both the first-first conductive pattern and the second-first conductive pattern” and “the first-first conductive pattern corresponding to the fourth region is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate”.
FIG. 2 of Han discloses a similar display device, comprising a second capacitor (C1) and a first capacitor (C2) such that the voltages of the first node N1, the second node N2, and the third node N3 are set as the same, thereby minimizing or reducing the leakage currents that flow to the second node N2 and the third node N3 from the first node N1 [0058]; the display device comprises a first-first conductive pattern (upper electrode of C2, connecting to ELVDD) and a second-first conductive pattern (upper electrode of C1 connecting to ELVDD) spaced apart from the first conductive pattern, wherein the first-first conductive pattern defining a first capacitor (C2) together with the fourth region (shared S/D of M3-1 and M3-2, where M3-1 = upper T2 of Noguchi, M3-2 = lower T2 of Noguchi) by partially overlapping the first active pattern (the fourth region as lower electrode of C2); the second-first conductive pattern defining a second capacitor (C1) together with the third region (shared S/D of M3-1 and M4-1, connecting the gate of M1, where M3-1 = upper T2 of Noguchi, M4-1 = T1 of Noguchi, M1 = T4 of Noguchi) by partially overlapping the first active pattern (the third region as the lower electrode of C1).
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Han, such that a second capacitor and a first capacitor are added to minimize or reduce the leakage currents [0058], thereby displaying the image of the desired luminance [0022]. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of minimizing leakage current (Para. 58 of Han).
Noguchi as modified by Han discloses the upper electrodes of the first capacitor, the second capacitor, and the storage capacitor are portions of a power supply voltage line, therefore, the first-first conductive pattern, the second-first conductive pattern, and the second conductive pattern are on a same layer; and a first light-emitting layer disposed on the first-first and second-first conductive patterns and the second conductive pattern.
Noguchi as modified by Han fails to explicitly disclose “a first gate electrode spaced apart from the first lower gate electrode on a same layer”; the “first-first conductive pattern disposed on the first gate electrode and the first lower gate electrode”; the first-first conductive pattern “partially overlapping the first active pattern in a thickness direction of the substrate”; the second-first conductive pattern “partially overlapping the first active pattern in the thickness direction of the substrate”; “a first power supply voltage is provided to both the first-first conductive pattern and the second-first conductive pattern” and “the first-first conductive pattern corresponding to the fourth region is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate”.
FIG. 6 (annotated above) of Wen discloses a similar display device, comprising a first gate electrode (G1) spaced apart from the first lower gate electrode (LG) on a same layer; a first-first conductive pattern (w11) disposed on the first gate electrode and the first lower gate electrode; a second-first conductive pattern (w12) on a same layer and partially overlapping the first active pattern in the thickness direction (vertical) of the substrate, and a first power supply voltage [0023] is provided to both the first-first conductive pattern and the second-first conductive pattern, wherein the first capacitor and the second capacitor are parasitic capacitors, and wherein the first-first conductive pattern corresponding to the fourth region (a4) is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Wen. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of forming cascade MOS devices (Para. 1 of Wen).
Regarding Claim 17
FIG. 6 of Wen discloses the first-first conductive pattern corresponding to the fourth region is spaced apart from any other electrodes both in the thickness direction of the substrate and in the direction perpendicular to the thickness direction of the substrate.
Claims 3, 4, 18 and 19 rejected under 35 U.S.C. 103 as being unpatentable over Noguchi, Han and Wen, in view of Ko (U.S. Patent Pub. No. 2014/0239270) of record.
Regarding Claim 3
Noguchi as modified by Han and Wen discloses Claim 1, comprising: a first power supply voltage line overlapping the second-first conductive pattern; and a second power supply voltage line overlapping the first-first conductive pattern, wherein the first power supply voltage line providing the first power supply voltage to the second-first conductive pattern; and the second power supply voltage line providing the first power supply voltage to the first-first conductive pattern.
Noguchi as modified by Han and Wen fails to explicitly disclose “the first power supply voltage line being connected to the second-first conductive pattern through a first contact hole” and “the second power supply voltage line being connected to the first-first conductive pattern through a second contact hole”.
FIG. 5 of Ko discloses a similar display device, comprising a first power supply voltage line (26) overlapping the second-first conductive pattern (Cst2), the first power supply voltage line being connected to the second-first conductive pattern through a first contact hole (49), the first power supply voltage line providing a first power supply voltage (ELVDD) to the second-first conductive pattern.
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Ko such that the display device comprising a second power supply voltage line overlapping the first-first conductive pattern, the second power supply voltage line being connected to the first-first conductive pattern through a second contact hole, the second power supply voltage line providing the first power supply voltage to the first-first conductive pattern, because mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144.04. The ordinary artisan would have been motivated to modify Noguchi in the above manner, because connecting two conductors at different levels through contact hole is common in the art.
Regarding Claim 4
FIG. 6 of Wen discloses the first power supply voltage line (42) overlaps the first active pattern.
Regarding Claim 18
Noguchi as modified by Han and Wen discloses Claim 16, comprising: a first power supply voltage line overlapping the second-first conductive pattern; and a second power supply voltage line overlapping the first-first conductive pattern, wherein the first power supply voltage line providing the first power supply voltage to the second-first conductive pattern; and the second power supply voltage line providing the first power supply voltage to the first-first conductive pattern.
Noguchi as modified by Han and Wen fails to explicitly disclose “the first power supply voltage line being connected to the second-first conductive pattern through a first contact hole” and “the second power supply voltage line being connected to the first-first conductive pattern through a second contact hole”.
FIG. 5 of Ko discloses a similar display device, comprising a first power supply voltage line (26) overlapping the second-first conductive pattern (Cst2), the first power supply voltage line being connected to the second-first conductive pattern through a first contact hole (49), the first power supply voltage line providing a first power supply voltage (ELVDD) to the second-first conductive pattern.
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Ko such that the display device comprising a second power supply voltage line overlapping the first-first conductive pattern, the second power supply voltage line being connected to the first-first conductive pattern through a second contact hole, the second power supply voltage line providing the first power supply voltage to the first-first conductive pattern, because mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144.04. The ordinary artisan would have been motivated to modify Noguchi in the above manner, because connecting two conductors at different levels through contact hole is common in the art.
Regarding Claim 19
FIG. 6 of Wen discloses the first power supply voltage line (42) overlaps the first active pattern.
Claims 5 and 20 rejected under 35 U.S.C. 103 as being unpatentable over Noguchi, Han, Wen and Ko, in view of Kim (U.S. Patent Pub. No. 2005/0116232) of record.
Regarding Claim 5
Noguchi as modified by Han, Wen and Ko discloses Claim 4.
Noguchi as modified by Han, Wen and Ko fails to disclose “a first data line spaced apart from the first power supply voltage line, wherein the first data line and the first power supply voltage line are disposed on a same layer”.
FIG. 4 of Kim discloses a similar display device, comprising a first data line (325) spaced apart from the first power supply voltage line (327), wherein the first data line and the first power supply voltage line are disposed on a same layer.
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Kim. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of simplifying manufacturing process (Para. 15 of Kim).
Regarding Claim 20
Noguchi as modified by Han, Wen and Ko discloses Claim 19.
Noguchi as modified by Han, Wen and Ko fails to disclose “a first data line spaced apart from the first power supply voltage line, wherein the first data line and the first power supply voltage line are disposed on a same layer”.
FIG. 4 of Kim discloses a similar display device, comprising a first data line (325) spaced apart from the first power supply voltage line (327), wherein the first data line and the first power supply voltage line are disposed on a same layer.
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Kim. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of simplifying manufacturing process (Para. 15 of Kim).
Claims 6-15 rejected under 35 U.S.C. 103 as being unpatentable over Noguchi, Han, Wen and Ko, in view of Shin (U.S. Patent Pub. No. 2014/0070184) of record.
Regarding Claim 6
Noguchi as modified by Han, Wen and Ko discloses Claim 3, wherein the second active pattern including a sub-first region, a sub-second region, a sub-third region, and a sub-fourth region; and a second lower gate electrode (another gate of T2) disposed on the second active pattern, and defining a sub-first transistor together with the sub-first and sub-second regions by partially overlapping the second active pattern.
Noguchi as modified by Han, Wen and Ko fails to disclose “a second active pattern spaced apart from the first active pattern on a same layer”.
FIGS. 4 and 5 of Shin discloses a similar display device, comprising a second active pattern (131c) spaced apart from the first active pattern (131a) on a same layer.
It would have been obvious to one of ordinary skill in the art before the effective filling of the claimed invention to modify the device of Noguchi, as taught by Shin. The ordinary artisan would have been motivated to modify Noguchi in the above manner for purpose of preventing spot generation in high resolution (Para. 7 of Shin).
Regarding Claim 7
FIG. 3 of Shin discloses a shape of the second active pattern is a substantially same as a shape of the first active pattern, and the second active pattern is spaced apart from the first active pattern in a first direction.
Regarding Claim 8
FIG. 8 of Noguchi discloses the first gate electrode extends in a first direction to overlap the second active pattern, and the first gate electrode defines a sub-second transistor together with the sub-third and sub-fourth regions and defines a sub-third transistor together with the sub-fourth and sub-second regions by partially overlapping the second active pattern; and the second conductive pattern extends in the first direction to overlap the second active pattern, and defines a sub-storage capacitor together with the second lower gate electrode by partially overlapping the second lower gate electrode.
Regarding Claim 9
Modified Noguchi discloses the first-first conductive pattern extends in a first direction to overlap the second active pattern, and defines a sub-second capacitor together with the sub-third region by partially overlapping the second active pattern.
Regarding Claim 10
Modified Noguchi discloses a first portion of the first-first conductive pattern overlaps a portion of the first active pattern, and a second portion of the first-first conductive pattern overlaps a portion of the second active pattern.
Regarding Claim 11
FIG. 8 of Noguchi discloses a third-first conductive pattern spaced apart from the first conductive pattern on a same layer, the third-first conductive pattern defining a sub-first capacitor together with the sub-fourth region by partially overlapping the second active pattern.
Regarding Claim 12
Modified Noguchi discloses the second-first conductive pattern, the first-first conductive pattern, and the third-first conductive pattern are sequentially arranged on the first and second active patterns in a first direction.
Regarding Claim 13
FIG. 4 of Shin discloses a second light-emitting layer (220) disposed on the first-first and third-first conductive patterns and the second conductive pattern.
Regarding Claim 14
FIG. 6 of Wen discloses the second power supply voltage line overlaps the second active pattern.
Regarding Claim 15
FIG. 8 of Noguchi discloses one of the pixels. It would have been obvious to one of ordinary skill in the art that a second data line spaced apart from the second power supply voltage line, wherein the second data line and the second power supply voltage line are disposed on a same layer, because mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144.04.
Pertinent Art
US 20030090599, 20060145960; CN 102315217, 1455632; KR 20100076603.
Response to Arguments
Applicant's arguments with respect to Wen have been considered but they are not persuasive. FIG. 6 (annotated above) of Wen discloses a first gate electrode (G1) spaced apart from the first lower gate electrode (LG) on a same layer; a first-first conductive pattern (w11) disposed on the first gate electrode and the first lower gate electrode; a second-first conductive pattern (w12) on a same layer and partially overlapping the first active pattern in the thickness direction (vertical) of the substrate, and a first power supply voltage [0023] is provided to both the first-first conductive pattern and the second-first conductive pattern, wherein the first capacitor and the second capacitor are parasitic capacitors, and wherein the first-first conductive pattern corresponding to the fourth region (a4) is entirely offset from the first gate electrode and the first lower gate electrode both in the thickness direction of the substrate and in a direction perpendicular to the thickness direction of the substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am-7pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897