Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on June 21, 2024, April 7, 2025, and June 3, 2025 were in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species I, Sub-Species A1 (claims 1-5 and 10-12) in the reply filed on 07/28/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (Pub. No.: US 2022/0302421 A1).
Regarding Claim 1, Choi et al. discloses a light emitting display device, comprising: a display panel including a display area and a component area, wherein the component area is surrounded by the display area and includes a plurality of optical sensor areas (Par. 0079; 0087, 0095, 0096; Figs. 1-3 – display area DA2, component area DA1; component area includes an optical sensor); and an optical element located on a back surface of the component area (Par. 0087, 0095, 0096; Fig. 5 – optical element 20), wherein the display area includes a pixel defining layer defining an opening that overlaps an anode in a plan view (Par. 0149-0151, 0179-0186; Fig. 5 together with Fig. 19 – pixel defining layer 123a (light-shielding insulating layer); opening 123aOP; anode 210 (pixel electrode)); a cathode covering the pixel defining layer (Par. 0183-0184; Fig. 5 together with Fig. 19 – cathode 230 (opposite electrode)); an encapsulation layer located on a top of the cathode (Par. 0253-0254; Fig. 5 together with Fig. 19 – encapsulation layer 300; cathode 230); and a color filter located on the encapsulation layer and overlapping the opening of the pixel defining layer in the plan view (Par. 0260-0265; Fig. 5 together with Fig. 19 – color filter 620a; encapsulation layer 300; opening of the pixel defining layer 123aOP); wherein the color filter and the pixel defining layer each extend to the component area and define an additional opening therein corresponding to each optical sensor area of the plurality of optical sensor areas (Par. 0199; 0249-0254; Fig. 5 together with Figs. 18-19 – additional opening of the color filter 610aOP2; for additional opening of the pixel defining layer see annotated Fig. 19 above), and
PNG
media_image1.png
652
756
media_image1.png
Greyscale
wherein an area of the additional opening of the color filter is smaller than an area of the additional opening of the pixel defining layer in the plan view such that a portion of the pixel defining layer is obscured by the color filter in the plan view in the each optical sensor area (see annotated Fig. 19 above).
Regarding Claim 2, Choi et al., as applied to claim 1. discloses the light emitting display device, wherein: a portion of the cathode located on an inclined surface of the pixel defining layer in the each optical sensor area is obscured by the color filter in the plan view (Fig. 19).
Regarding Claim 4, Choi et al., as applied to claim 2, discloses the light emitting display device, wherein: the pixel defining layer is a black pixel defining layer, and a light blocking layer is not located on an upper portion of the black pixel defining layer (Par. 0188; Fig. 19 – light blocking layer 610a (light shielding layer) is not located at least on a part of an upper portion of the black pixel defining layer 123a in the plan view).
Regarding Claim 12, Choi et al., as applied to claim 2, discloses the light emitting display device, wherein: a buffer area is located between the component area and the display area (see annotated Fig. 19 below - reads the limitation under BRI).
PNG
media_image2.png
494
552
media_image2.png
Greyscale
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as obvious over Choi et al. (Pub. No.: US 2022/0302421 A1), as applied to claim 2.
Regarding Claim 3, Choi et al., as applied to claim 2, does not explicitly disclose the light emitting display device, wherein: an interval between the additional opening of the pixel defining layer and the additional opening of the color filter is 1 micrometer (µm) to 2 µm. Choi et al. clearly shows an interval between the additional opening of the pixel defining layer and the additional opening of the color filter (Fig. 19). However, Choi et al. stops short of providing an optimum range for the said interval. However, it is understood that the said interval is a result effective variable. Too large an interval will reduce the display area and too short an interval will cause visual artifacts. Choi et al. discloses the claimed invention except for the light emitting display device, wherein: an interval between the additional opening of the pixel defining layer and the additional opening of the color filter is 1 micrometer (µm) to 2 µm. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the light emitting display device, wherein: an interval between the additional opening of the pixel defining layer and the additional opening of the color filter is 1 micrometer (µm) to 2 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Allowable Subject Matter
Claims 5 and 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Woo et al. (Pub. No.: US 2022/0416216 A1) – This prior art teaches a light emitting display device, comprising: a display panel including a display area (DA) and a component area (OPS), wherein the component area is surrounded by the display area and includes a plurality of optical sensor areas; and an optical element located on a back surface of the component area, wherein the display area includes a pixel defining layer (380) defining an opening (OP) that overlaps an anode in a plan view; a cathode covering the pixel defining layer; an encapsulation layer (400) located on a top of the cathode; and a color filter (230) located on the encapsulation layer and overlapping the opening of the pixel defining layer in the plan view, Fig. 24).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED I GHEYAS whose telephone number is (571)272-0592. The examiner can normally be reached on Monday-Friday from 8:30 AM - 5:30 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley, can be reached at telephone number (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
08/05/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
Prosecution Insights